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Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs
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128
techlibs/altera_intel/cycloneiv/cells_comb_cycloneiv.v
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128
techlibs/altera_intel/cycloneiv/cells_comb_cycloneiv.v
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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module VCC (output V);
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assign V = 1'b1;
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endmodule // VCC
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module GND (output G);
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assign G = 1'b0;
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endmodule // GND
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/* Altera Cyclone IV (GX) devices Input Buffer Primitive */
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module cycloneiv_io_ibuf (output o, input i, input ibar);
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assign ibar = ibar;
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assign o = i;
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endmodule // fiftyfivenm_io_ibuf
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/* Altera Cyclone IV (GX) devices Output Buffer Primitive */
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module cycloneiv_io_obuf (output o, input i, input oe);
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assign o = i;
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assign oe = oe;
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endmodule // fiftyfivenm_io_obuf
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/* Altera MAX10 4-input non-fracturable LUT Primitive */
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module cycloneiv_lcell_comb (output combout, cout,
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input dataa, datab, datac, datad, cin);
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/* Internal parameters which define the behaviour
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of the LUT primitive.
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lut_mask define the lut function, can be expressed in 16-digit bin or hex.
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sum_lutc_input define the type of LUT (combinational | arithmetic).
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dont_touch for retiming || carry options.
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lpm_type for WYSIWYG */
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parameter lut_mask = 16'hFFFF;
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parameter dont_touch = "off";
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parameter lpm_type = "cycloneiv_lcell_comb";
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parameter sum_lutc_input = "datac";
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reg [1:0] lut_type;
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reg cout_rt;
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reg combout_rt;
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wire dataa_w;
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wire datab_w;
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wire datac_w;
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wire datad_w;
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wire cin_w;
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assign dataa_w = dataa;
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assign datab_w = datab;
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assign datac_w = datac;
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assign datad_w = datad;
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function lut_data;
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input [15:0] mask;
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input dataa, datab, datac, datad;
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reg [7:0] s3;
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reg [3:0] s2;
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reg [1:0] s1;
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begin
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s3 = datad ? mask[15:8] : mask[7:0];
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s2 = datac ? s3[7:4] : s3[3:0];
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s1 = datab ? s2[3:2] : s2[1:0];
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lut_data = dataa ? s1[1] : s1[0];
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end
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endfunction
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initial begin
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if (sum_lutc_input == "datac") lut_type = 0;
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else
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if (sum_lutc_input == "cin") lut_type = 1;
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else begin
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$error("Error in sum_lutc_input. Parameter %s is not a valid value.\n", sum_lutc_input);
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$finish();
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end
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end
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always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin
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if (lut_type == 0) begin // logic function
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combout_rt = lut_data(lut_mask, dataa_w, datab_w,
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datac_w, datad_w);
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end
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else if (lut_type == 1) begin // arithmetic function
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combout_rt = lut_data(lut_mask, dataa_w, datab_w,
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cin_w, datad_w);
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end
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cout_rt = lut_data(lut_mask, dataa_w, datab_w, cin_w, 'b0);
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end
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assign combout = combout_rt & 1'b1;
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assign cout = cout_rt & 1'b1;
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endmodule // cycloneiv_lcell_comb
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/* Altera Cyclone IV Flip-Flop Primitive */
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// TODO: Implement advanced simulation functions
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module dffeas ( output q,
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input d, clk, clrn, prn, ena,
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input asdata, aload, sclr, sload );
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parameter power_up="dontcare";
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parameter is_wysiwyg="false";
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reg q;
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always @(posedge clk)
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q <= d;
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endmodule
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61
techlibs/altera_intel/cycloneiv/cells_map_cycloneiv.v
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61
techlibs/altera_intel/cycloneiv/cells_map_cycloneiv.v
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@ -0,0 +1,61 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// Flip-flop D
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module \$_DFF_P_ (input D, input C, output Q);
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parameter WYSIWYG="TRUE";
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dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
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endmodule //
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// Input buffer map
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module \$__inpad (input I, output O);
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cycloneiv_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
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endmodule
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// Output buffer map
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module \$__outpad (input I, output O);
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cycloneiv_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
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endmodule
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// LUT Map
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/* 0 -> datac
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1 -> cin */
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module \$lut (A, Y);
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parameter WIDTH = 0;
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parameter LUT = 0;
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input [WIDTH-1:0] A;
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output Y;
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generate
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if (WIDTH == 1) begin
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assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
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end else
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if (WIDTH == 2) begin
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cycloneiv_lcell_comb #(.lut_mask({4{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1));
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end else
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if(WIDTH == 3) begin
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cycloneiv_lcell_comb #(.lut_mask({2{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(1'b1));
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end else
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if(WIDTH == 4) begin
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cycloneiv_lcell_comb #(.lut_mask(LUT), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(A[3]));
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end else
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wire _TECHMAP_FAIL_ = 1;
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endgenerate
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endmodule //
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