mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-27 10:55:51 +00:00
Code Activity

Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs

Browse source
This commit is contained in:
dh73 2017-04-05 23:01:29 -05:00
parent fcb274a564
commit c27dcc1e47
25 changed files with 2255 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

5
examples/intel/asicworld_lfsr/runme_presynth Executable file
View file

@ -0,0 +1,5 @@
#!/bin/bash
iverilog -o presynth lfsr_updown_tb.v lfsr_updown.v &&\
vvp -N presynth