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Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs

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dh73 2017-04-05 23:01:29 -05:00
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6
examples/intel/asicworld_lfsr/README Normal file
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Source of the files:
http://www.asic-world.com/examples/verilog/lfsr.html
Run first: runme_presynth
Generate output netlist with run_max10 or run_cycloneiv
Then, check with: runme_postsynth