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Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs

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dh73 2017-04-05 23:01:29 -05:00
parent fcb274a564
commit c27dcc1e47
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examples/intel/MAX10/runme_postsynth Normal file
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#!/bin/bash
iverilog -D POST_IMPL -o verif_post -s tb_top tb_top.v top.vqm $(yosys-config --datdir/altera_intel/max10/cells_comb_max10.v)
vvp -N verif_post