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Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs

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dh73 2017-04-05 23:01:29 -05:00
parent fcb274a564
commit c27dcc1e47
25 changed files with 2255 additions and 0 deletions
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examples/intel/DE2i-150/quartus_compile/de2i.qpf Normal file
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QUARTUS_VERSION = "16.1"
# Revisions
PROJECT_REVISION = "de2i"

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examples/intel/DE2i-150/quartus_compile/de2i.qsf Normal file
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examples/intel/DE2i-150/quartus_compile/runme_quartus Normal file
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#!/bin/bash
export REV="de2i"
quartus_map -c $REV top && \
quartus_fit -c $REV top && \
quartus_asm -c $REV top

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examples/intel/DE2i-150/run_cycloneiv Normal file
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#/bin/env bash
yosys -p "synth_intel -family cycloneiv -top top -vout top.vqm" top.v sevenseg.v

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examples/intel/DE2i-150/sevenseg.v Normal file
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module sevenseg ( output reg [6:0] HEX0,
input [3:0] SW );
always @(*) begin
case(SW)
4'h1: HEX0 = 7'b1111001;
4'h2: HEX0 = 7'b0100100;
4'h3: HEX0 = 7'b0110000;
4'h4: HEX0 = 7'b0011001;
4'h5: HEX0 = 7'b0010010;
4'h6: HEX0 = 7'b0000010;
4'h7: HEX0 = 7'b1111000;
4'h8: HEX0 = 7'b0000000;
4'h9: HEX0 = 7'b0011000;
4'ha: HEX0 = 7'b0001000;
4'hb: HEX0 = 7'b0000011;
4'hc: HEX0 = 7'b1000110;
4'hd: HEX0 = 7'b0100001;
4'he: HEX0 = 7'b0000110;
4'hf: HEX0 = 7'b0001110;
4'h0: HEX0 = 7'b1000000;
endcase // case (SW)
end
endmodule

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examples/intel/DE2i-150/top.v Normal file
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`default_nettype none
module top ( output wire [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7,
input wire [15:0] SW );
sevenseg UUD0 (.HEX0(HEX0), .SW(4'h7));
sevenseg UUD1 (.HEX0(HEX1), .SW(4'h1));
sevenseg UUD2 (.HEX0(HEX2), .SW(4'h0));
sevenseg UUD3 (.HEX0(HEX3), .SW(4'h2));
sevenseg UUD4 (.HEX0(HEX4), .SW(SW[3:0]));
sevenseg UUD5 (.HEX0(HEX5), .SW(SW[7:4]));
sevenseg UUD6 (.HEX0(HEX6), .SW(SW[11:8]));
sevenseg UUD7 (.HEX0(HEX7), .SW(SW[15:12]));
endmodule