Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs

examples/intel/DE2i-150/quartus_compile/de2i.qpf

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+QUARTUS_VERSION = "16.1"
+# Revisions
+
+PROJECT_REVISION = "de2i"

examples/intel/DE2i-150/quartus_compile/runme_quartus

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+#!/bin/bash
+
+export REV="de2i"
+
+quartus_map -c $REV top && \
+    quartus_fit -c $REV top && \
+	    quartus_asm -c $REV top

examples/intel/DE2i-150/run_cycloneiv

@@ -0,0 +1,2 @@
+#/bin/env bash
+yosys -p "synth_intel -family cycloneiv -top top -vout top.vqm" top.v sevenseg.v

examples/intel/DE2i-150/sevenseg.v

@@ -0,0 +1,25 @@
+module sevenseg ( output reg [6:0] HEX0,
+                  input      [3:0] SW );
+
+   always @(*) begin
+     case(SW)
+        4'h1: HEX0 = 7'b1111001;	
+	4'h2: HEX0 = 7'b0100100; 	
+	4'h3: HEX0 = 7'b0110000; 	
+	4'h4: HEX0 = 7'b0011001; 	
+	4'h5: HEX0 = 7'b0010010; 	
+	4'h6: HEX0 = 7'b0000010; 	
+	4'h7: HEX0 = 7'b1111000; 	
+	4'h8: HEX0 = 7'b0000000; 	
+	4'h9: HEX0 = 7'b0011000; 	
+	4'ha: HEX0 = 7'b0001000;
+	4'hb: HEX0 = 7'b0000011;
+	4'hc: HEX0 = 7'b1000110;
+	4'hd: HEX0 = 7'b0100001;
+	4'he: HEX0 = 7'b0000110;
+	4'hf: HEX0 = 7'b0001110;
+	4'h0: HEX0 = 7'b1000000;
+     endcase // case (SW)
+   end 
+   
+endmodule

examples/intel/DE2i-150/top.v

@@ -0,0 +1,15 @@
+`default_nettype none
+module top ( output wire [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7,
+             input  wire [15:0] SW );
+             
+  
+    sevenseg UUD0 (.HEX0(HEX0), .SW(4'h7));
+    sevenseg UUD1 (.HEX0(HEX1), .SW(4'h1));
+    sevenseg UUD2 (.HEX0(HEX2), .SW(4'h0));
+    sevenseg UUD3 (.HEX0(HEX3), .SW(4'h2));
+    sevenseg UUD4 (.HEX0(HEX4), .SW(SW[3:0]));
+    sevenseg UUD5 (.HEX0(HEX5), .SW(SW[7:4]));
+    sevenseg UUD6 (.HEX0(HEX6), .SW(SW[11:8]));
+    sevenseg UUD7 (.HEX0(HEX7), .SW(SW[15:12]));
+    
+endmodule

examples/intel/MAX10/run_max10

@@ -0,0 +1 @@
+yosys -p "synth_intel -family max10 -top top -vout top.vqm" top.v sevenseg.v

examples/intel/MAX10/runme_postsynth

@@ -0,0 +1,5 @@
+#!/bin/bash
+
+iverilog -D POST_IMPL -o verif_post -s tb_top tb_top.v top.vqm $(yosys-config --datdir/altera_intel/max10/cells_comb_max10.v)
+vvp -N verif_post
+

examples/intel/MAX10/sevenseg.v

@@ -0,0 +1,25 @@
+module sevenseg ( output reg [6:0] HEX0,
+                  input      [3:0] SW );
+
+   always @(*) begin
+     case(SW)
+        4'h1: HEX0 = 7'b1111001;	
+	4'h2: HEX0 = 7'b0100100; 	
+	4'h3: HEX0 = 7'b0110000; 	
+	4'h4: HEX0 = 7'b0011001; 	
+	4'h5: HEX0 = 7'b0010010; 	
+	4'h6: HEX0 = 7'b0000010; 	
+	4'h7: HEX0 = 7'b1111000; 	
+	4'h8: HEX0 = 7'b0000000; 	
+	4'h9: HEX0 = 7'b0011000; 	
+	4'ha: HEX0 = 7'b0001000;
+	4'hb: HEX0 = 7'b0000011;
+	4'hc: HEX0 = 7'b1000110;
+	4'hd: HEX0 = 7'b0100001;
+	4'he: HEX0 = 7'b0000110;
+	4'hf: HEX0 = 7'b0001110;
+	4'h0: HEX0 = 7'b1000000;
+     endcase // case (SW)
+   end 
+   
+endmodule

examples/intel/MAX10/top.v

@@ -0,0 +1,15 @@
+`default_nettype none
+module top ( output wire [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7,
+             input  wire [15:0] SW );
+             
+  
+    sevenseg UUD0 (.HEX0(HEX0), .SW(4'h7));
+    sevenseg UUD1 (.HEX0(HEX1), .SW(4'h1));
+    sevenseg UUD2 (.HEX0(HEX2), .SW(4'h0));
+    sevenseg UUD3 (.HEX0(HEX3), .SW(4'h2));
+    sevenseg UUD4 (.HEX0(HEX4), .SW(SW[3:0]));
+    sevenseg UUD5 (.HEX0(HEX5), .SW(SW[7:4]));
+    sevenseg UUD6 (.HEX0(HEX6), .SW(SW[11:8]));
+    sevenseg UUD7 (.HEX0(HEX7), .SW(SW[15:12]));
+    
+endmodule

examples/intel/asicworld_lfsr/README

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+Source of the files:
+http://www.asic-world.com/examples/verilog/lfsr.html
+
+Run first: runme_presynth
+Generate output netlist with run_max10 or run_cycloneiv
+Then, check with: runme_postsynth

examples/intel/asicworld_lfsr/lfsr_updown.v

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+`default_nettype none
+module lfsr_updown (
+clk       ,   // Clock input
+reset     ,   // Reset input
+enable    ,   // Enable input
+up_down   ,   // Up Down input
+count     ,   // Count output
+overflow      // Overflow output
+);
+
+ input clk;
+ input reset;
+ input enable; 
+ input up_down;
+
+ output [7 : 0] count;
+ output overflow;
+
+ reg [7 : 0] count;
+
+ assign overflow = (up_down) ? (count == {{7{1'b0}}, 1'b1}) : 
+                               (count == {1'b1, {7{1'b0}}}) ;
+
+ always @(posedge clk)
+ if (reset) 
+    count <= {7{1'b0}};
+ else if (enable) begin
+    if (up_down) begin
+      count <= {~(^(count & 8'b01100011)),count[7:1]};
+    end else begin
+      count <= {count[5:0],~(^(count &  8'b10110001))};
+    end
+ end
+
+endmodule

examples/intel/asicworld_lfsr/lfsr_updown_tb.v

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+module tb();
+ reg clk;
+ reg reset;
+ reg enable;
+ reg up_down;
+
+ wire [7 : 0] count;
+ wire overflow;
+
+initial begin
+  $monitor("rst %b en %b updown %b cnt %b overflow %b",
+     reset,enable,up_down,count, overflow);
+  clk = 0;
+  reset = 1;
+  enable = 0;
+  up_down = 0;
+  #10 reset = 0;
+  #1 enable = 1;
+  #20 up_down = 1;
+  #30 $finish;
+end
+
+always #1 clk = ~clk;
+
+lfsr_updown U(
+.clk      ( clk      ),
+.reset    ( reset    ),
+.enable   ( enable   ),
+.up_down  ( up_down  ),
+.count    ( count    ),
+.overflow ( overflow )
+);
+
+endmodule 

examples/intel/asicworld_lfsr/run_cycloneiv

@@ -0,0 +1,2 @@
+#!/bin/env bash
+yosys -p "synth_intel -family cycloneiv -top lfsr_updown -vout top.vqm" lfsr_updown.v

examples/intel/asicworld_lfsr/run_max10

@@ -0,0 +1,2 @@
+#!/bin/env bash
+yosys -p "synth_intel -family max10 -top lfsr_updown -vout top.vqm" lfsr_updown.v

examples/intel/asicworld_lfsr/runme_postsynth

@@ -0,0 +1,5 @@
+#!/bin/bash
+
+iverilog -D POST_IMPL -o verif_post -s tb lfsr_updown_tb.v top.vqm $(yosys-config --datdir/altera_intel/max10/cells_comb_max10.v)
+vvp -N verif_post
+

examples/intel/asicworld_lfsr/runme_presynth

@@ -0,0 +1,5 @@
+#!/bin/bash
+
+iverilog -o presynth lfsr_updown_tb.v lfsr_updown.v &&\
+
+vvp -N presynth