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xilinx to use abc_map.v with -max_iter 1

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This commit is contained in:
Eddie Hung 2019-08-20 19:47:11 -07:00
parent 6b1b03d9f7
commit c26c556384
6 changed files with 26 additions and 171 deletions
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2
techlibs/xilinx/synth_xilinx.cc
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@ -391,7 +391,7 @@ struct SynthXilinxPass : public ScriptPass
if (family != "xc7")
log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
run("read_verilog -icells -lib +/xilinx/abc_model.v");
run("techmap -map +/xilinx/abc_map.v");
run("techmap -map +/xilinx/abc_map.v -max_iter 1");
if (nowidelut)
run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
else