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xilinx to use abc_map.v with -max_iter 1

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This commit is contained in:
Eddie Hung 2019-08-20 19:47:11 -07:00
parent 6b1b03d9f7
commit c26c556384
6 changed files with 26 additions and 171 deletions
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9
techlibs/xilinx/cells_sim.v
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@ -298,7 +298,8 @@ module FDPE_1 ((* abc_arrival=303 *) output reg Q,
endmodule
module RAM32X1D (
output DPO, SPO,
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
(* abc_arrival=11530 *) output DPO, SPO,
input D,
input WCLK,
input WE,
@ -317,7 +318,8 @@ module RAM32X1D (
endmodule
module RAM64X1D (
output DPO, SPO,
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
(* abc_arrival=1153 *) output DPO, SPO,
input D,
input WCLK,
input WE,
@ -336,7 +338,8 @@ module RAM64X1D (
endmodule
module RAM128X1D (
output DPO, SPO,
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
(* abc_arrival=1153 *) output DPO, SPO,
input D,
input WCLK,
input WE,