sf2: suport $alu gate and ARI1 implementation

techlibs/sf2/arith_map.v

@@ -17,5 +17,53 @@
  *
  */
 
+(* techmap_celltype = "$alu" *)
+module \$__SF2_ALU (A, B, CI, BI, X, Y, CO);
+	parameter A_SIGNED = 0;
+	parameter B_SIGNED = 0;
+	parameter A_WIDTH = 1;
+	parameter B_WIDTH = 1;
+	parameter Y_WIDTH = 1;
+
+	(* force_downto *)
+	input [A_WIDTH-1:0] A;
+	(* force_downto *)
+	input [B_WIDTH-1:0] B;
+	(* force_downto *)
+	output [Y_WIDTH-1:0] X, Y;
+
+	input CI, BI;
+	(* force_downto *)
+	output [Y_WIDTH-1:0] CO;
+
+	wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+
+	(* force_downto *)
+	wire [Y_WIDTH-1:0] AA, BB;
+	\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(AA));
+	\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(BB));
+
+	(* force_downto *)
+	wire [Y_WIDTH-1:0] C = {CO, CI};
+
+	genvar i;
+	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
+		ARI1 #(
+			// G = F1 = A[i] & (B[i]^BI)
+			// Y = F0 = A[i]^B[i]^BI
+			// P = Y
+			//		 ADCB
+			.INIT(20'b 01_11_0010_1000_1001_0110)
+		) carry (
+			.A(1'b0),
+			.B(AA[i]),
+			.C(BB[i]),
+			.D(BI),
+			.FCI(C[i]),
+			.Y(X[i]),
+			.S(Y[i]),
+			.FCO(CO[i])
+		);
+	end endgenerate
+endmodule
 
-// nothing here yet

techlibs/sf2/cells_sim.v

@@ -152,7 +152,22 @@ module SLE (
 	assign Q = LAT ? q_latch : q_ff;
 endmodule
 
-// module AR1
+module ARI1 (
+	input A, B, C, D, FCI,
+	output Y, S, FCO
+);
+	parameter [19:0] INIT = 20'h0;
+	wire [2:0] Fsel = {D, C, B};
+	wire F0 = INIT[Fsel];
+	wire F1 = INIT[8 + Fsel];
+	wire Yout = A ? F1 : F0;
+	assign Y = Yout;
+	wire S = FCI ^ Yout;
+	wire G = INIT[16] ? (INIT[17] ? F1 : F0) : INIT[17];
+	wire P = INIT[19] ? 1'b1 : (INIT[18] ? Yout : 1'b0);
+	assign FCO = P ? FCI : G;
+endmodule
+
 // module FCEND_BUFF
 // module FCINIT_BUFF
 // module FLASH_FREEZE