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Fix SYNTHESIS always being defined in Verilog frontend

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georgerennie 2020-12-01 01:37:19 +00:00
parent 2116c58581
commit c1f6ce8b33
2 changed files with 3 additions and 1 deletions
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frontends/verilog/preproc.cc
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@ -321,7 +321,6 @@ struct define_body_t
define_map_t::define_map_t()
{
add("YOSYS", "1");
add(formal_mode ? "FORMAL" : "SYNTHESIS", "1");
}
// We must define this destructor here (rather than relying on the default), because we need to