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peeopt.shiftmul: Add a signedness check.

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Fixes #2332.
This commit is contained in:
Marcelina Kościelnicka 2020-08-05 21:01:20 +02:00
parent c39ebe6ae0
commit c1ed1c28be
2 changed files with 12 additions and 5 deletions
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6
passes/pmgen/peepopt_shiftmul.pmg
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@ -31,22 +31,18 @@ match mul
select mul->type.in($mul)
select port(mul, \A).is_fully_const() || port(mul, \B).is_fully_const()
index <SigSpec> port(mul, \Y) === shamt
filter !param(mul, \A_SIGNED).as_bool()
endmatch
code
{
IdString const_factor_port = port(mul, \A).is_fully_const() ? \A : \B;
IdString const_factor_signed = const_factor_port == \A ? \A_SIGNED : \B_SIGNED;
Const const_factor_cnst = port(mul, const_factor_port).as_const();
int const_factor = const_factor_cnst.as_int();
if (GetSize(const_factor_cnst) == 0)
reject;
if (const_factor_cnst.bits[GetSize(const_factor_cnst)-1] != State::S0 &&
param(mul, const_factor_signed).as_bool())
reject;
if (GetSize(const_factor_cnst) > 20)
reject;

11
tests/techmap/bug2332.ys Normal file
View file

@ -0,0 +1,11 @@
read_verilog <<EOT
module top(input [31:0] a, input signed [2:0] x, output [2:0] o);
wire [5:0] t = x * 3;
assign o = a >> t;
endmodule
EOT
wreduce
equiv_opt -assert peepopt