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peeopt.shiftmul: Add a signedness check.

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Fixes #2332.
This commit is contained in:
Marcelina Kościelnicka 2020-08-05 21:01:20 +02:00
parent c39ebe6ae0
commit c1ed1c28be
2 changed files with 12 additions and 5 deletions
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11
tests/techmap/bug2332.ys Normal file
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read_verilog <<EOT
module top(input [31:0] a, input signed [2:0] x, output [2:0] o);
wire [5:0] t = x * 3;
assign o = a >> t;
endmodule
EOT
wreduce
equiv_opt -assert peepopt