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verilog: impose limit on maximum expression width

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Designs with unreasonably wide expressions would previously get stuck
allocating memory forever.
This commit is contained in:
Zachary Snow 2021-03-04 15:08:16 -05:00
parent 7d2097b005
commit c18ddbcd82
3 changed files with 39 additions and 0 deletions
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6
frontends/ast/genrtlil.cc
View file

@ -1000,6 +1000,12 @@ void AstNode::detectSignWidth(int &width_hint, bool &sign_hint, bool *found_real
if (found_real)
*found_real = false;
detectSignWidthWorker(width_hint, sign_hint, found_real);
constexpr int kWidthLimit = 1 << 24;
if (width_hint >= kWidthLimit)
log_file_error(filename, location.first_line,
"Expression width %d exceeds implementation limit of %d!\n",
width_hint, kWidthLimit);
}
static void check_unique_id(RTLIL::Module *module, RTLIL::IdString id,

17
tests/verilog/absurd_width.ys Normal file
View file

@ -0,0 +1,17 @@
logger -expect error "Expression width 1073741824 exceeds implementation limit of 16777216!" 1
read_verilog <<EOF
module top(
input inp,
output out
);
assign out =
{1024 {
{1024 {
{1024 {
inp
}}
}}
}}
;
endmodule
EOF

16
tests/verilog/absurd_width_const.ys Normal file
View file

@ -0,0 +1,16 @@
logger -expect error "Expression width 1073741824 exceeds implementation limit of 16777216!" 1
read_verilog <<EOF
module top(
output out
);
assign out =
{1024 {
{1024 {
{1024 {
1'b1
}}
}}
}}
;
endmodule
EOF