mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-13 04:28:18 +00:00
Code Activity

D is 25 bits not 24 bits wide

Browse source
This commit is contained in:
Eddie Hung 2019-09-19 15:55:49 -07:00
parent b88f0f6450
commit c15a35db84
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
techlibs/xilinx/dsp_map.v
View file

@ -32,7 +32,7 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y);
.A({{5{A[24]}}, A}), .A({{5{A[24]}}, A}),
.B(B), .B(B),
.C(48'b0), .C(48'b0),
.D(24'b0), .D(25'b0),
.P(P_48), .P(P_48),
.INMODE(5'b00000), .INMODE(5'b00000),