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https://github.com/YosysHQ/yosys
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rtlil: add textual roundtrip test
This commit is contained in:
Emil J. Tywoniak
parent
d7a80c6165
commit
c12b485135
7 changed files with 1554 additions and 0 deletions
1
Makefile
1
Makefile
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@ -874,6 +874,7 @@ MK_TEST_DIRS += tests/sim
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MK_TEST_DIRS += tests/svtypes
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MK_TEST_DIRS += tests/svtypes
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MK_TEST_DIRS += tests/techmap
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MK_TEST_DIRS += tests/techmap
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MK_TEST_DIRS += tests/various
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MK_TEST_DIRS += tests/various
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MK_TEST_DIRS += tests/rtlil
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ifeq ($(ENABLE_VERIFIC),1)
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ifeq ($(ENABLE_VERIFIC),1)
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ifneq ($(YOSYS_NOVERIFIC),1)
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ifneq ($(YOSYS_NOVERIFIC),1)
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MK_TEST_DIRS += tests/verific
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MK_TEST_DIRS += tests/verific
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2
tests/rtlil/.gitignore
vendored
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2
tests/rtlil/.gitignore
vendored
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@ -0,0 +1,2 @@
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*.tmp.il
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*.tmp.il.bak
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40
tests/rtlil/everything.v
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40
tests/rtlil/everything.v
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@ -0,0 +1,40 @@
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module alu(
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input clk,
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input [7:0] A,
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input [7:0] B,
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input [3:0] operation,
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output reg [7:0] result,
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output reg CF,
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output reg ZF,
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output reg SF
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);
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localparam ALU_OP_ADD = 4'b0000;
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localparam ALU_OP_SUB = 4'b0001;
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reg [8:0] tmp;
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always @(posedge clk)
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begin
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case (operation)
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ALU_OP_ADD :
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tmp = A + B;
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ALU_OP_SUB :
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tmp = A - B;
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endcase
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CF <= tmp[8];
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ZF <= tmp[7:0] == 0;
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SF <= tmp[7];
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result <= tmp[7:0];
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end
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endmodule
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module foo(
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input [7:0] a, input [7:0] b, output [7:0] y
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);
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wire [7:0] bb;
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assign b = bb;
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assign y = a + bb;
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endmodule
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283
tests/rtlil/roundtrip-text.ref.il
Normal file
283
tests/rtlil/roundtrip-text.ref.il
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@ -0,0 +1,283 @@
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autoidx 15
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attribute \src "everything.v:1.1-32.10"
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attribute \cells_not_processed 1
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module \alu
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attribute \src "everything.v:2.8-2.11"
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wire input 1 \clk
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attribute \src "everything.v:3.14-3.15"
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wire width 8 input 2 \A
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attribute \src "everything.v:4.14-4.15"
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wire width 8 input 3 \B
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attribute \src "everything.v:5.14-5.23"
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wire width 4 input 4 \operation
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attribute \src "everything.v:6.19-6.25"
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wire width 8 output 5 \result
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attribute \src "everything.v:7.13-7.15"
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wire output 6 \CF
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attribute \src "everything.v:8.13-8.15"
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wire output 7 \ZF
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attribute \src "everything.v:9.13-9.15"
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wire output 8 \SF
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attribute \src "everything.v:15.12-15.15"
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wire width 9 \tmp
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attribute \src "everything.v:17.2-31.5"
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wire width 8 $0\result[7:0]
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attribute \src "everything.v:17.2-31.5"
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wire $0\CF[0:0]
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attribute \src "everything.v:17.2-31.5"
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wire $0\ZF[0:0]
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attribute \src "everything.v:17.2-31.5"
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wire $0\SF[0:0]
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attribute \src "everything.v:17.2-31.5"
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wire width 9 $0\tmp[8:0]
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attribute \src "everything.v:17.2-31.5"
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wire width 9 $1\tmp[8:0]
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attribute \src "everything.v:21.11-21.16"
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wire width 9 $add$everything.v:21$2_Y
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attribute \src "everything.v:23.11-23.16"
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wire width 9 $sub$everything.v:23$3_Y
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attribute \src "everything.v:27.9-27.22"
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wire $eq$everything.v:27$4_Y
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attribute \src "everything.v:21.11-21.16"
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cell $add $add$everything.v:21$2
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parameter \A_SIGNED 0
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parameter \B_SIGNED 0
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parameter \A_WIDTH 8
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parameter \B_WIDTH 8
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parameter \Y_WIDTH 9
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connect \A \A
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connect \B \B
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connect \Y $add$everything.v:21$2_Y
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end
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attribute \src "everything.v:23.11-23.16"
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cell $sub $sub$everything.v:23$3
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parameter \A_SIGNED 0
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parameter \B_SIGNED 0
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parameter \A_WIDTH 8
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parameter \B_WIDTH 8
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parameter \Y_WIDTH 9
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connect \A \A
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connect \B \B
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connect \Y $sub$everything.v:23$3_Y
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end
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attribute \src "everything.v:27.9-27.22"
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cell $eq $eq$everything.v:27$4
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parameter \A_SIGNED 0
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parameter \B_SIGNED 0
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parameter \A_WIDTH 8
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parameter \B_WIDTH 32
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parameter \Y_WIDTH 1
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connect \A $1\tmp[8:0] [7:0]
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connect \B 0
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connect \Y $eq$everything.v:27$4_Y
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end
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attribute \src "everything.v:17.2-31.5"
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process $proc$everything.v:17$1
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assign { } { }
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assign { } { }
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assign { } { }
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assign { } { }
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assign { } { }
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assign $0\tmp[8:0] $1\tmp[8:0]
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assign $0\CF[0:0] $1\tmp[8:0] [8]
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assign $0\ZF[0:0] $eq$everything.v:27$4_Y
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assign $0\SF[0:0] $1\tmp[8:0] [7]
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assign $0\result[7:0] $1\tmp[8:0] [7:0]
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attribute \src "everything.v:19.3-24.10"
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switch \operation
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attribute \src "everything.v:19.19-19.19"
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case 4'0000
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assign { } { }
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assign $1\tmp[8:0] $add$everything.v:21$2_Y
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attribute \src "everything.v:21.17-21.17"
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case 4'0001
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assign { } { }
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assign $1\tmp[8:0] $sub$everything.v:23$3_Y
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case
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assign $1\tmp[8:0] \tmp
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end
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sync posedge \clk
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update \result $0\result[7:0]
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update \CF $0\CF[0:0]
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update \ZF $0\ZF[0:0]
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update \SF $0\SF[0:0]
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update \tmp $0\tmp[8:0]
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end
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end
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attribute \src "everything.v:34.1-40.10"
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attribute \cells_not_processed 1
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module \foo
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attribute \src "everything.v:35.17-35.18"
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wire width 8 input 1 \a
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attribute \src "everything.v:35.32-35.33"
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wire width 8 input 2 \b
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attribute \src "everything.v:35.48-35.49"
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wire width 8 output 3 \y
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attribute \src "everything.v:37.16-37.18"
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wire width 8 \bb
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attribute \src "everything.v:39.16-39.22"
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wire width 8 $add$everything.v:39$5_Y
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attribute \src "everything.v:39.16-39.22"
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cell $add $add$everything.v:39$5
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parameter \A_SIGNED 0
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parameter \B_SIGNED 0
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parameter \A_WIDTH 8
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parameter \B_WIDTH 8
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parameter \Y_WIDTH 8
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connect \A \a
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connect \B \bb
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connect \Y $add$everything.v:39$5_Y
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end
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connect \b \bb
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connect \y $add$everything.v:39$5_Y
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end
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attribute \cells_not_processed 1
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attribute \src "everything.v:1.1-32.10"
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module \zzz
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attribute \src "everything.v:27.9-27.22"
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wire $eq$everything.v:27$4_Y
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attribute \src "everything.v:23.11-23.16"
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wire width 9 $sub$everything.v:23$3_Y
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attribute \src "everything.v:21.11-21.16"
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wire width 9 $add$everything.v:21$2_Y
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attribute \src "everything.v:17.2-31.5"
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wire width 9 $1\tmp[8:0]
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attribute \src "everything.v:17.2-31.5"
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wire width 9 $0\tmp[8:0]
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attribute \src "everything.v:17.2-31.5"
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wire $0\SF[0:0]
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attribute \src "everything.v:17.2-31.5"
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wire $0\ZF[0:0]
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attribute \src "everything.v:17.2-31.5"
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wire $0\CF[0:0]
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attribute \src "everything.v:17.2-31.5"
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wire width 8 $0\result[7:0]
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attribute \src "everything.v:15.12-15.15"
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wire width 9 \tmp
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attribute \src "everything.v:9.13-9.15"
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wire output 8 \SF
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attribute \src "everything.v:8.13-8.15"
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wire output 7 \ZF
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attribute \src "everything.v:7.13-7.15"
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wire output 6 \CF
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attribute \src "everything.v:6.19-6.25"
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wire width 8 output 5 \result
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attribute \src "everything.v:5.14-5.23"
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wire width 4 input 4 \operation
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attribute \src "everything.v:4.14-4.15"
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wire width 8 input 3 \B
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attribute \src "everything.v:3.14-3.15"
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wire width 8 input 2 \A
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attribute \src "everything.v:2.8-2.11"
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wire input 1 \clk
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wire $procmux$8_CMP
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wire width 9 $procmux$7_Y
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wire $procmux$9_CMP
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attribute \src "everything.v:27.9-27.22"
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cell $logic_not $eq$everything.v:27$4
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parameter \A_SIGNED 0
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parameter \Y_WIDTH 1
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parameter \A_WIDTH 8
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connect \A $1\tmp[8:0] [7:0]
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connect \Y $eq$everything.v:27$4_Y
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end
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attribute \src "everything.v:23.11-23.16"
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cell $sub $sub$everything.v:23$3
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parameter \A_SIGNED 0
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parameter \B_SIGNED 0
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parameter \A_WIDTH 8
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parameter \B_WIDTH 8
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parameter \Y_WIDTH 9
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connect \A \A
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connect \B \B
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connect \Y $sub$everything.v:23$3_Y
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end
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attribute \src "everything.v:21.11-21.16"
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cell $add $add$everything.v:21$2
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parameter \A_SIGNED 0
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parameter \B_SIGNED 0
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parameter \A_WIDTH 8
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parameter \B_WIDTH 8
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parameter \Y_WIDTH 9
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connect \A \A
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connect \B \B
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connect \Y $add$everything.v:21$2_Y
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end
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attribute \src "everything.v:19.3-24.10"
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attribute \full_case 1
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cell $eq $procmux$8_CMP0
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parameter \A_SIGNED 0
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parameter \B_SIGNED 0
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parameter \A_WIDTH 4
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parameter \B_WIDTH 4
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parameter \Y_WIDTH 1
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connect \A \operation
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connect \B 4'0001
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connect \Y $procmux$8_CMP
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end
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attribute \src "everything.v:19.3-24.10"
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attribute \full_case 1
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cell $pmux $procmux$7
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parameter \WIDTH 9
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parameter \S_WIDTH 2
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connect \A \tmp
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connect \B { $add$everything.v:21$2_Y $sub$everything.v:23$3_Y }
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connect \S { $procmux$9_CMP $procmux$8_CMP }
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connect \Y $procmux$7_Y
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end
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attribute \src "everything.v:19.3-24.10"
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attribute \full_case 1
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cell $logic_not $procmux$9_CMP0
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parameter \A_SIGNED 0
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parameter \Y_WIDTH 1
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parameter \A_WIDTH 4
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connect \A \operation
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connect \Y $procmux$9_CMP
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end
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attribute \src "everything.v:17.2-31.5"
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cell $dff $procdff$10
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parameter \WIDTH 8
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parameter \CLK_POLARITY 1'1
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connect \D $procmux$7_Y [7:0]
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connect \Q \result
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connect \CLK \clk
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end
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attribute \src "everything.v:17.2-31.5"
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cell $dff $procdff$11
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parameter \WIDTH 1
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parameter \CLK_POLARITY 1'1
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connect \D $procmux$7_Y [8]
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connect \Q \CF
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connect \CLK \clk
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end
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attribute \src "everything.v:17.2-31.5"
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cell $dff $procdff$12
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parameter \WIDTH 1
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parameter \CLK_POLARITY 1'1
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connect \D $eq$everything.v:27$4_Y
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connect \Q \ZF
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connect \CLK \clk
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end
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attribute \src "everything.v:17.2-31.5"
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cell $dff $procdff$13
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parameter \WIDTH 1
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parameter \CLK_POLARITY 1'1
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connect \D $procmux$7_Y [7]
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connect \Q \SF
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connect \CLK \clk
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end
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attribute \src "everything.v:17.2-31.5"
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cell $dff $procdff$14
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parameter \WIDTH 9
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parameter \CLK_POLARITY 1'1
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connect \D $procmux$7_Y
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connect \Q \tmp
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connect \CLK \clk
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end
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connect $0\result[7:0] $1\tmp[8:0] [7:0]
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connect $0\SF[0:0] $1\tmp[8:0] [7]
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connect $0\ZF[0:0] $eq$everything.v:27$4_Y
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connect $0\CF[0:0] $1\tmp[8:0] [8]
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connect $0\tmp[8:0] $1\tmp[8:0]
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connect $1\tmp[8:0] $procmux$7_Y
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end
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30
tests/rtlil/roundtrip-text.sh
Normal file
30
tests/rtlil/roundtrip-text.sh
Normal file
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@ -0,0 +1,30 @@
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set -euo pipefail
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YS=../../yosys
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# write_rtlil and dump are equivalent
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$YS -p "read_verilog -sv everything.v; copy alu zzz; proc zzz; dump -o roundtrip-text.dump.tmp.il; write_rtlil roundtrip-text.write.tmp.il"
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sed '/^$/d' -i.bak roundtrip-text.dump.tmp.il
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sed '/^$/d' -i.bak roundtrip-text.write.tmp.il
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# Trim first line ("Generated by Yosys ...")
|
||||||
|
tail -n +2 roundtrip-text.write.tmp.il > roundtrip-text.write-nogen.tmp.il
|
||||||
|
diff roundtrip-text.dump.tmp.il roundtrip-text.write-nogen.tmp.il
|
||||||
|
diff roundtrip-text.dump.tmp.il roundtrip-text.ref.il
|
||||||
|
|
||||||
|
# Loading and writing it out again doesn't change the RTLIL
|
||||||
|
$YS -p "read_rtlil roundtrip-text.dump.tmp.il; write_rtlil roundtrip-text.reload.tmp.il"
|
||||||
|
sed '/^$/d' -i.bak roundtrip-text.reload.tmp.il
|
||||||
|
tail -n +2 roundtrip-text.reload.tmp.il > roundtrip-text.reload-nogen.tmp.il
|
||||||
|
diff roundtrip-text.dump.tmp.il roundtrip-text.reload-nogen.tmp.il
|
||||||
|
|
||||||
|
# Hashing differences don't change the RTLIL
|
||||||
|
$YS --hash-seed=2345678 -p "read_rtlil roundtrip-text.dump.tmp.il; write_rtlil roundtrip-text.reload-hash.tmp.il"
|
||||||
|
sed '/^$/d' -i.bak roundtrip-text.reload-hash.tmp.il
|
||||||
|
tail -n +2 roundtrip-text.reload-hash.tmp.il > roundtrip-text.reload-hash-nogen.tmp.il
|
||||||
|
diff roundtrip-text.dump.tmp.il roundtrip-text.reload-hash-nogen.tmp.il
|
||||||
|
|
||||||
|
echo "Without ABC, we don't get any irreproducibility and can pin that"
|
||||||
|
echo "Has this test case started failing for you? Consider updating the reference"
|
||||||
|
$YS -p "read_verilog -sv everything.v; synth -noabc; write_rtlil roundtrip-text.synth.tmp.il"
|
||||||
|
sed '/^$/d' -i.bak roundtrip-text.synth.tmp.il
|
||||||
|
tail -n +2 roundtrip-text.synth.tmp.il > roundtrip-text.synth-nogen.tmp.il
|
||||||
|
diff roundtrip-text.synth-nogen.tmp.il roundtrip-text.synth.ref.il
|
||||||
1194
tests/rtlil/roundtrip-text.synth.ref.il
Normal file
1194
tests/rtlil/roundtrip-text.synth.ref.il
Normal file
File diff suppressed because it is too large
Load diff
4
tests/rtlil/run-test.sh
Executable file
4
tests/rtlil/run-test.sh
Executable file
|
|
@ -0,0 +1,4 @@
|
||||||
|
#!/usr/bin/env bash
|
||||||
|
set -eu
|
||||||
|
source ../gen-tests-makefile.sh
|
||||||
|
generate_mk --bash
|
||||||
Loading…
Add table
Add a link
Reference in a new issue