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abc: sort stats

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Emil J. Tywoniak 2024-10-04 13:20:15 +02:00
parent 953508f6d2
commit c10b3f57e1
1 changed files with 1 additions and 0 deletions
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passes/techmap/abc.cc
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@ -1411,6 +1411,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
module->connect(conn);
}
cell_stats.sort();
for (auto &it : cell_stats)
log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second);
int in_wires = 0, out_wires = 0;