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Split mux tests per type

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This commit is contained in:
Miodrag Milanovic 2019-10-04 13:05:16 +02:00
parent 1b80489486
commit c0fa6f3e1a
2 changed files with 36 additions and 38 deletions
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39
tests/efinix/mux.ys
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@ -1,8 +1,41 @@
read_verilog mux.v
design -save read
proc
flatten
hierarchy -top mux2
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 13 t:EFX_LUT4
cd mux2 # Constrain all select calls below inside the top module
select -assert-count 1 t:EFX_LUT4
select -assert-none t:EFX_LUT4 %% t:* %D
design -load read
proc
hierarchy -top mux4
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module
select -assert-count 2 t:EFX_LUT4
select -assert-none t:EFX_LUT4 %% t:* %D
design -load read
proc
hierarchy -top mux8
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
select -assert-count 5 t:EFX_LUT4
select -assert-none t:EFX_LUT4 %% t:* %D
design -load read
proc
hierarchy -top mux16
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
select -assert-count 12 t:EFX_LUT4
select -assert-none t:EFX_LUT4 %% t:* %D