mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-09 23:53:26 +00:00
Code Activity

Add missing items in CHANGELOG

Browse source
This commit is contained in:
Miodrag Milanovic 2021-10-29 13:31:41 +02:00
parent 55f07fe56f
commit c0edfa8788
1 changed files with 6 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

6
CHANGELOG
View file

@ -16,6 +16,12 @@ Yosys 0.10 .. Yosys 0.10-dev
- Fixed an issue where connecting a slice covering the entirety of a signed - Fixed an issue where connecting a slice covering the entirety of a signed
signal to a cell input would cause a failed assertion signal to a cell input would cause a failed assertion
* Verific support
- Importer support for {PRIM,WIDE_OPER}_DFF
- Importer support for PRIM_BUFIF1
- Option to use Verific without VHDL support
- Importer support for {PRIM,WIDE_OPER}_DLATCH{,RS}
Yosys 0.9 .. Yosys 0.10 Yosys 0.9 .. Yosys 0.10
-------------------------- --------------------------