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Added "port_directions" to write_json output

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This commit is contained in:
Clifford Wolf 2015-04-06 01:49:58 +02:00
parent a1c62b79d5
commit c0e2b3eb11
1 changed files with 20 additions and 0 deletions
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20
backends/json/json.cc
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@ -137,6 +137,19 @@ struct JsonWriter
f << stringf(" \"attributes\": {"); f << stringf(" \"attributes\": {");
write_parameters(c->attributes); write_parameters(c->attributes);
f << stringf("\n },\n"); f << stringf("\n },\n");
if (c->known()) {
f << stringf(" \"port_directions\": {");
bool first2 = true;
for (auto &conn : c->connections()) {
string direction = "output";
if (c->input(conn.first))
direction = c->output(conn.first) ? "inout" : "input";
f << stringf("%s\n", first2 ? "" : ",");
f << stringf(" %s: \"%s\"", get_name(conn.first).c_str(), direction.c_str());
first2 = false;
}
f << stringf("\n },\n");
}
f << stringf(" \"connections\": {"); f << stringf(" \"connections\": {");
bool first2 = true; bool first2 = true;
for (auto &conn : c->connections()) { for (auto &conn : c->connections()) {
@ -240,6 +253,10 @@ struct JsonBackend : public Backend {
log(" <attribute_name>: <attribute_value>,\n"); log(" <attribute_name>: <attribute_value>,\n");
log(" ...\n"); log(" ...\n");
log(" },\n"); log(" },\n");
log(" \"port_directions\": {\n");
log(" <port_name>: <\"input\" | \"output\" | \"inout\">,\n");
log(" ...\n");
log(" },\n");
log(" \"connections\": {\n"); log(" \"connections\": {\n");
log(" <port_name>: <bit_vector>,\n"); log(" <port_name>: <bit_vector>,\n");
log(" ...\n"); log(" ...\n");
@ -256,6 +273,9 @@ struct JsonBackend : public Backend {
log("The \"hide_name\" fields are set to 1 when the name of this cell or net is\n"); log("The \"hide_name\" fields are set to 1 when the name of this cell or net is\n");
log("automatically created and is likely not of interest for a regular user.\n"); log("automatically created and is likely not of interest for a regular user.\n");
log("\n"); log("\n");
log("The \"port_directions\" section is only included for cells for which the\n");
log("interface is known.\n");
log("\n");
log("Module and cell ports and nets can be single bit wide or vectors of multiple\n"); log("Module and cell ports and nets can be single bit wide or vectors of multiple\n");
log("bits. Each individual signal bit is assigned a unique integer. The <bit_vector>\n"); log("bits. Each individual signal bit is assigned a unique integer. The <bit_vector>\n");
log("values referenced above are vectors of this integers. Signal bits that are\n"); log("values referenced above are vectors of this integers. Signal bits that are\n");