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https://github.com/YosysHQ/yosys
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Add fileinfo to firrtl backend for assignments and non-instance cells
This commit is contained in:
Sahand Kashani
parent
3e04e29dec
commit
c0b2a9af2e
1 changed files with 30 additions and 21 deletions
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@ -261,7 +261,7 @@ struct FirrtlWorker
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}
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}
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// We need a default constructor for the dict insert.
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memory() : pCell(0), read_latency(0), write_latency(1), init_file(""), init_file_srcFileSpec(""){}
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memory() : pCell(0), read_latency(0), write_latency(1), init_file(""), init_file_srcFileSpec(""){}
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const char *atLine() {
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if (srcLine == "") {
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@ -494,7 +494,7 @@ struct FirrtlWorker
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{
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static Const ndef(0, 0);
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// Is this cell is a module instance?
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// Is this cell is a module instance?
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if (cell->type[0] != '$')
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{
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process_instance(cell, wire_exprs);
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@ -512,11 +512,12 @@ struct FirrtlWorker
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string primop;
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bool always_uint = false;
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string y_id = make_id(cell->name);
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std::string cellFileinfo = getFileinfo(cell->attributes);
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if (cell->type.in("$not", "$logic_not", "$neg", "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_bool", "$reduce_xnor"))
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{
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string a_expr = make_expr(cell->getPort("\\A"));
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wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
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wire_decls.push_back(stringf(" wire %s: UInt<%d> %s\n", y_id.c_str(), y_width, cellFileinfo.c_str()));
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if (a_signed) {
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a_expr = "asSInt(" + a_expr + ")";
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@ -535,16 +536,16 @@ struct FirrtlWorker
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firrtl_is_signed = true; // Result of "neg" is signed (an SInt).
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firrtl_width = a_width;
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} else if (cell->type == "$logic_not") {
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primop = "eq";
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a_expr = stringf("%s, UInt(0)", a_expr.c_str());
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}
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primop = "eq";
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a_expr = stringf("%s, UInt(0)", a_expr.c_str());
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}
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else if (cell->type == "$reduce_and") primop = "andr";
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else if (cell->type == "$reduce_or") primop = "orr";
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else if (cell->type == "$reduce_xor") primop = "xorr";
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else if (cell->type == "$reduce_xnor") {
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primop = "not";
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a_expr = stringf("xorr(%s)", a_expr.c_str());
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}
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primop = "not";
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a_expr = stringf("xorr(%s)", a_expr.c_str());
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}
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else if (cell->type == "$reduce_bool") {
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primop = "neq";
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// Use the sign of the a_expr and its width as the type (UInt/SInt) and width of the comparand.
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@ -556,18 +557,19 @@ struct FirrtlWorker
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if ((firrtl_is_signed && !always_uint))
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expr = stringf("asUInt(%s)", expr.c_str());
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cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str()));
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cell_exprs.push_back(stringf(" %s <= %s %s\n", y_id.c_str(), expr.c_str(), cellFileinfo.c_str()));
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register_reverse_wire_map(y_id, cell->getPort("\\Y"));
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continue;
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}
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if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$xor", "$xnor", "$and", "$or", "$eq", "$eqx",
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"$gt", "$ge", "$lt", "$le", "$ne", "$nex", "$shr", "$sshr", "$sshl", "$shl",
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"$logic_and", "$logic_or", "$pow"))
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"$gt", "$ge", "$lt", "$le", "$ne", "$nex", "$shr", "$sshr", "$sshl", "$shl",
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"$logic_and", "$logic_or", "$pow"))
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{
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string a_expr = make_expr(cell->getPort("\\A"));
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string b_expr = make_expr(cell->getPort("\\B"));
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wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
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std::string cellFileinfo = getFileinfo(cell->attributes);
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wire_decls.push_back(stringf(" wire %s: UInt<%d> %s\n", y_id.c_str(), y_width, cellFileinfo.c_str()));
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if (a_signed) {
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a_expr = "asSInt(" + a_expr + ")";
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@ -650,7 +652,7 @@ struct FirrtlWorker
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primop = "eq";
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always_uint = true;
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firrtl_width = 1;
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}
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}
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else if ((cell->type == "$ne") | (cell->type == "$nex")) {
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primop = "neq";
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always_uint = true;
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@ -783,7 +785,7 @@ struct FirrtlWorker
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if ((firrtl_is_signed && !always_uint))
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expr = stringf("asUInt(%s)", expr.c_str());
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cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str()));
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cell_exprs.push_back(stringf(" %s <= %s %s\n", y_id.c_str(), expr.c_str(), cellFileinfo.c_str()));
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register_reverse_wire_map(y_id, cell->getPort("\\Y"));
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continue;
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@ -795,11 +797,11 @@ struct FirrtlWorker
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string a_expr = make_expr(cell->getPort("\\A"));
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string b_expr = make_expr(cell->getPort("\\B"));
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string s_expr = make_expr(cell->getPort("\\S"));
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wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), width));
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wire_decls.push_back(stringf(" wire %s: UInt<%d> %s\n", y_id.c_str(), width, cellFileinfo.c_str()));
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string expr = stringf("mux(%s, %s, %s)", s_expr.c_str(), b_expr.c_str(), a_expr.c_str());
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cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str()));
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cell_exprs.push_back(stringf(" %s <= %s %s\n", y_id.c_str(), expr.c_str(), cellFileinfo.c_str()));
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register_reverse_wire_map(y_id, cell->getPort("\\Y"));
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continue;
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@ -938,9 +940,9 @@ struct FirrtlWorker
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string expr = make_expr(cell->getPort("\\D"));
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string clk_expr = "asClock(" + make_expr(cell->getPort("\\CLK")) + ")";
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wire_decls.push_back(stringf(" reg %s: UInt<%d>, %s\n", y_id.c_str(), width, clk_expr.c_str()));
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wire_decls.push_back(stringf(" reg %s: UInt<%d>, %s %s\n", y_id.c_str(), width, clk_expr.c_str(), cellFileinfo.c_str()));
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cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str()));
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cell_exprs.push_back(stringf(" %s <= %s %s\n", y_id.c_str(), expr.c_str(), cellFileinfo.c_str()));
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register_reverse_wire_map(y_id, cell->getPort("\\Q"));
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continue;
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@ -1030,6 +1032,7 @@ struct FirrtlWorker
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for (auto wire : module->wires())
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{
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string expr;
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std::string wireFileinfo = getFileinfo(wire->attributes);
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if (wire->port_input)
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continue;
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@ -1088,14 +1091,20 @@ struct FirrtlWorker
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if (is_valid) {
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if (make_unconn_id) {
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wire_decls.push_back(stringf(" wire %s: UInt<1>\n", unconn_id.c_str()));
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wire_decls.push_back(stringf(" wire %s: UInt<1> %s\n", unconn_id.c_str(), wireFileinfo.c_str()));
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// `invalid` is a firrtl construction for simulation so we will not
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// tag it with a @[fileinfo] tag as it doesn't directly correspond to
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// a specific line of verilog code.
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wire_decls.push_back(stringf(" %s is invalid\n", unconn_id.c_str()));
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}
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wire_exprs.push_back(stringf(" %s <= %s\n", make_id(wire->name), expr.c_str()));
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wire_exprs.push_back(stringf(" %s <= %s %s\n", make_id(wire->name), expr.c_str(), wireFileinfo.c_str()));
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} else {
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if (make_unconn_id) {
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unconn_id.clear();
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}
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// `invalid` is a firrtl construction for simulation so we will not
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// tag it with a @[fileinfo] tag as it doesn't directly correspond to
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// a specific line of verilog code.
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wire_decls.push_back(stringf(" %s is invalid\n", make_id(wire->name)));
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}
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}
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