mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-27 10:55:51 +00:00
Code Activity

Added support for "assign" statements in abc vlparse

Browse source
This commit is contained in:
Clifford Wolf 2013-06-15 13:50:38 +02:00
parent 6ef8c6fb8a
commit c09b66b2a1
2 changed files with 39 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

8
passes/abc/abc.cc
View file

@ -572,6 +572,14 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
}
}
for (auto conn : mapped_mod->connections) {
if (!conn.first.is_fully_const())
conn.first = RTLIL::SigSpec(module->wires[remap_name(conn.first.chunks[0].wire->name)]);
if (!conn.second.is_fully_const())
conn.second = RTLIL::SigSpec(module->wires[remap_name(conn.second.chunks[0].wire->name)]);
module->connections.push_back(conn);
}
for (auto &it : cell_stats)
log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second);
int in_wires = 0, out_wires = 0;