mirror of
https://github.com/YosysHQ/yosys
synced 2025-08-19 01:32:20 +00:00
Removed RTLIL::SigSpec::optimize()
This commit is contained in:
parent
8fd8e4a468
commit
c094c53de8
24 changed files with 15 additions and 181 deletions
|
@ -241,8 +241,6 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
|
|||
new_conn.second.append_bit(s2[i]);
|
||||
}
|
||||
if (new_conn.first.size() > 0) {
|
||||
new_conn.first.optimize();
|
||||
new_conn.second.optimize();
|
||||
used_signals.add(new_conn.first);
|
||||
used_signals.add(new_conn.second);
|
||||
module->connections.push_back(new_conn);
|
||||
|
|
|
@ -481,8 +481,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
|
|||
}
|
||||
|
||||
if (new_a.size() < a.size() || new_b.size() < b.size()) {
|
||||
new_a.optimize();
|
||||
new_b.optimize();
|
||||
cell->connections["\\A"] = new_a;
|
||||
cell->connections["\\B"] = new_b;
|
||||
cell->parameters["\\A_WIDTH"] = new_a.size();
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue