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https://github.com/YosysHQ/yosys
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Removed RTLIL::SigSpec::optimize()
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parent
8fd8e4a468
commit
c094c53de8
24 changed files with 15 additions and 181 deletions
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@ -42,13 +42,10 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
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eq_sig_a.append(ctrl_in.extract(j, 1));
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eq_sig_b.append(RTLIL::SigSpec(pattern.bits[j]));
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}
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eq_sig_a.optimize();
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eq_sig_b.optimize();
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for (int in_state : it.second)
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if (fullstate_cache.count(in_state) == 0)
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or_sig.append(RTLIL::SigSpec(state_onehot, in_state));
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or_sig.optimize();
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if (or_sig.size() == 0)
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continue;
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@ -218,8 +215,6 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
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sig_a.append(RTLIL::SigSpec(state_wire, j));
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sig_b.append(RTLIL::SigSpec(state.bits[j]));
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}
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sig_a.optimize();
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sig_b.optimize();
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if (sig_b == RTLIL::SigSpec(RTLIL::State::S1))
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{
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