mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-10 13:10:51 +00:00
Code Activity

Removed RTLIL::SigSpec::optimize()

Browse source
This commit is contained in:
Clifford Wolf 2014-07-23 20:32:28 +02:00
parent 8fd8e4a468
commit c094c53de8
24 changed files with 15 additions and 181 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/cmds/splice.cc
View file

@ -82,7 +82,6 @@ struct SpliceWorker
module->add(cell);
}
new_sig.optimize();
sliced_signals_cache[sig] = new_sig;
return new_sig;
@ -143,7 +142,6 @@ struct SpliceWorker
module->add(cell);
}
new_sig.optimize();
spliced_signals_cache[sig] = new_sig;
log(" Created spliced signal: %s -> %s\n", log_signal(sig), log_signal(new_sig));