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Removed RTLIL::SigSpec::optimize()
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parent
8fd8e4a468
commit
c094c53de8
24 changed files with 15 additions and 181 deletions
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@ -34,10 +34,8 @@ struct BitPatternPool
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width = sig.size();
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if (width > 0) {
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std::vector<RTLIL::State> pattern(width);
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sig.optimize();
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for (int i = 0; i < width; i++) {
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RTLIL::SigSpec s = sig.extract(i, 1);
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s.optimize();
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assert(s.chunks().size() == 1);
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if (s.chunks()[0].wire == NULL && s.chunks()[0].data.bits[0] <= RTLIL::State::S1)
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pattern[i] = s.chunks()[0].data.bits[0];
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@ -61,7 +59,6 @@ struct BitPatternPool
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bits_t sig2bits(RTLIL::SigSpec sig)
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{
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sig.optimize();
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assert(sig.is_fully_const());
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assert(sig.chunks().size() == 1);
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bits_t bits = sig.chunks()[0].data.bits;
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