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Removed RTLIL::SigSpec::optimize()

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This commit is contained in:
Clifford Wolf 2014-07-23 20:32:28 +02:00
parent 8fd8e4a468
commit c094c53de8
24 changed files with 15 additions and 181 deletions
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3
backends/verilog/verilog_backend.cc
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@ -133,7 +133,6 @@ std::string id(std::string internal_id, bool may_rename = true)
bool is_reg_wire(RTLIL::SigSpec sig, std::string &reg_name)
{
sig.optimize();
if (sig.chunks().size() != 1 || sig.chunks()[0].wire == NULL)
return false;
if (reg_wires.count(sig.chunks()[0].wire->name) == 0)
@ -303,7 +302,6 @@ std::string cellname(RTLIL::Cell *cell)
if (sig.size() != 1 || sig.is_fully_const())
goto no_special_reg_name;
sig.optimize();
RTLIL::Wire *wire = sig.chunks()[0].wire;
if (wire->name[0] != '\\')
@ -909,7 +907,6 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module)
continue;
RTLIL::SigSpec sig = cell->connections["\\Q"];
sig.optimize();
if (sig.chunks().size() == 1 && sig.chunks()[0].wire)
for (int i = 0; i < sig.chunks()[0].width; i++)