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Call equiv_opt with -multiclock and -assert

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This commit is contained in:
Eddie Hung 2019-12-31 18:39:32 -08:00
parent 22fe931c86
commit c082329af3
5 changed files with 5 additions and 5 deletions
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tests/arch/ice40/counter.ys
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@ -2,7 +2,7 @@ read_verilog ../common/counter.v
hierarchy -top top
proc
flatten
equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check
equiv_opt -assert -multiclock -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 6 t:SB_CARRY