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Make out of tree build testing possible

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This commit is contained in:
Miodrag Milanovic 2026-05-19 14:26:07 +02:00
parent 5c6de04467
commit c0779f488a
37 changed files with 131 additions and 119 deletions
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8
tests/various/async.sh
View file

@ -1,9 +1,9 @@
#!/usr/bin/env bash
set -ex
../../yosys -q -o async_syn.v -r uut -p 'synth; rename uut syn' async.v
../../yosys -q -o async_prp.v -r uut -p 'prep; rename uut prp' async.v
../../yosys -q -o async_a2s.v -r uut -p 'prep; async2sync; rename uut a2s' async.v
../../yosys -q -o async_ffl.v -r uut -p 'prep; clk2fflogic; rename uut ffl' async.v
${YOSYS} -q -o async_syn.v -r uut -p 'synth; rename uut syn' async.v
${YOSYS} -q -o async_prp.v -r uut -p 'prep; rename uut prp' async.v
${YOSYS} -q -o async_a2s.v -r uut -p 'prep; async2sync; rename uut a2s' async.v
${YOSYS} -q -o async_ffl.v -r uut -p 'prep; clk2fflogic; rename uut ffl' async.v
iverilog -o async_sim -DTESTBENCH async.v async_???.v
vvp -N async_sim > async.out
tail async.out

8
tests/various/chparam.sh
View file

@ -35,18 +35,18 @@ module top #(
endmodule
EOT
if ../../yosys -q -p 'verific -sv chparam1.sv'; then
../../yosys -q -p 'verific -sv chparam1.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
if ${YOSYS} -q -p 'verific -sv chparam1.sv'; then
${YOSYS} -q -p 'verific -sv chparam1.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
-p 'async2sync' \
-p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \
-p 'sat -falsify -prove-asserts -show-ports -set din[0] 0'
../../yosys -q -p 'verific -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
${YOSYS} -q -p 'verific -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
-p 'async2sync' \
-p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \
-p 'sat -falsify -prove-asserts -show-ports -set din[0] 0'
fi
../../yosys -q -p 'read_verilog -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
${YOSYS} -q -p 'read_verilog -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
-p 'async2sync' \
-p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \
-p 'sat -falsify -prove-asserts -show-ports -set din[0] 0'

4
tests/various/clk2fflogic_effects.sh
View file

@ -3,14 +3,14 @@ set -e
# TODO: when sim gets native $check support, remove the -DNO_ASSERT here
echo Running yosys sim
../../yosys -q -p "
${YOSYS} -q -p "
read_verilog -formal -DNO_ASSERT clk2fflogic_effects.sv
hierarchy -top top; proc;;
tee -q -o clk2fflogic_effects.sim.log sim -q -n 32
"
echo Running yosys clk2fflogic sim
../../yosys -q -p "
${YOSYS} -q -p "
read_verilog -formal clk2fflogic_effects.sv
hierarchy -top top; proc;;
clk2fflogic;;

8
tests/various/ezcmdline_plugin.sh
View file

@ -4,9 +4,9 @@ DIR=$(cd "$(dirname "$0")" && pwd)
BASEDIR=$(cd "$DIR/../.." && pwd)
rm -f "$DIR/ezcmdline_plugin.so"
chmod +x "$DIR/ezcmdline_dummy_solver"
CXXFLAGS=$("$BASEDIR/yosys-config" --cxxflags)
DATDIR=$("$BASEDIR/yosys-config" --datdir)
CXXFLAGS=$(${YOSYS_CONFIG} --cxxflags)
DATDIR=$(${YOSYS_CONFIG} --datdir)
DATDIR=${DATDIR//\//\\\/}
CXXFLAGS=${CXXFLAGS//$DATDIR/..\/..\/share}
"$BASEDIR/yosys-config" --exec --cxx ${CXXFLAGS} -I"$BASEDIR" --ldflags -shared -o "$DIR/ezcmdline_plugin.so" "$DIR/ezcmdline_plugin.cc"
"$BASEDIR/yosys" -m "$DIR/ezcmdline_plugin.so" -p "ezcmdline_test -cmd $DIR/ezcmdline_dummy_solver" | grep -q "ezcmdline_test passed!"
${YOSYS_CONFIG} --exec --cxx ${CXXFLAGS} -I"$BASEDIR" --ldflags -shared -o "$DIR/ezcmdline_plugin.so" "$DIR/ezcmdline_plugin.cc"
${YOSYS} -m "$DIR/ezcmdline_plugin.so" -p "ezcmdline_test -cmd $DIR/ezcmdline_dummy_solver" | grep -q "ezcmdline_test passed!"

6
tests/various/hierarchy.sh
View file

@ -4,7 +4,7 @@
set -e
echo -n " TOP first - "
../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module"
${YOSYS} -s - <<- EOY | grep "Automatically selected TOP as design top module"
read_verilog << EOV
module TOP(a, y);
input a;
@ -23,7 +23,7 @@ echo -n " TOP first - "
EOY
echo -n " TOP last - "
../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module"
${YOSYS} -s - <<- EOY | grep "Automatically selected TOP as design top module"
read_verilog << EOV
module aoi12(a, y);
input a;
@ -42,7 +42,7 @@ echo -n " TOP last - "
EOY
echo -n " no explicit top - "
../../yosys -s - <<- EOY | grep "Automatically selected noTop as design top module."
${YOSYS} -s - <<- EOY | grep "Automatically selected noTop as design top module."
read_verilog << EOV
module aoi12(a, y);
input a;

2
tests/various/logger_cmd_error.sh
View file

@ -2,7 +2,7 @@
trap 'echo "ERROR in logger_cmd_error.sh" >&2; exit 1' ERR
(../../yosys -v 3 -C <<EOF
(${YOSYS} -v 3 -C <<EOF
yosys -import
hierarchy -top nonexistent
EOF

2
tests/various/logger_fail.sh
View file

@ -10,7 +10,7 @@ runTest() {
want="$2"
shift 2
echo "running '$desc' with args $@"
output=`../../yosys -q "$@" 2>&1`
output=`${YOSYS} -q "$@" 2>&1`
if [ $? -ne 1 ]; then
fail "exit code for '$desc' was not 1"
fi

10
tests/various/plugin.sh
View file

@ -1,12 +1,12 @@
set -e
rm -f plugin.so
rm -rf plugin_search
CXXFLAGS=$(../../yosys-config --cxxflags)
DATDIR=$(../../yosys-config --datdir)
CXXFLAGS=$(${YOSYS_CONFIG} --cxxflags)
DATDIR=$(${YOSYS_CONFIG} --datdir)
DATDIR=${DATDIR//\//\\\/}
CXXFLAGS=${CXXFLAGS//$DATDIR/..\/..\/share}
../../yosys-config --exec --cxx ${CXXFLAGS} --ldflags -shared -o plugin.so plugin.cc
../../yosys -m ./plugin.so -p "test" | grep -q "Plugin test passed!"
${YOSYS_CONFIG} --exec --cxx ${CXXFLAGS} --ldflags -shared -o plugin.so plugin.cc
${YOSYS} -m ./plugin.so -p "test" | grep -q "Plugin test passed!"
mkdir -p plugin_search
mv plugin.so plugin_search/plugin.so
YOSYS_PLUGIN_PATH=$PWD/plugin_search ../../yosys -m plugin.so -p "test" | grep -q "Plugin test passed!"
YOSYS_PLUGIN_PATH=$PWD/plugin_search ${YOSYS} -m plugin.so -p "test" | grep -q "Plugin test passed!"

20
tests/various/sv_implicit_ports.sh
View file

@ -3,7 +3,7 @@
trap 'echo "ERROR in sv_implicit_ports.sh" >&2; exit 1' ERR
# Simple case
../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
${YOSYS} -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
module add(input [7:0] a, input [7:0] b, output [7:0] q);
assign q = a + b;
endmodule
@ -15,7 +15,7 @@ endmodule
EOT
# Generate block
../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
${YOSYS} -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
module add(input [7:0] a, input [7:0] b, output [7:0] q);
assign q = a + b;
endmodule
@ -31,7 +31,7 @@ endmodule
EOT
# Missing wire
((../../yosys -f "verilog -sv" -qp "hierarchy -top top" - || true) <<EOT
((${YOSYS} -f "verilog -sv" -qp "hierarchy -top top" - || true) <<EOT
module add(input [7:0] a, input [7:0] b, output [7:0] q);
assign q = a + b;
endmodule
@ -43,7 +43,7 @@ EOT
) 2>&1 | grep -F "ERROR: No matching wire for implicit port connection \`b' of cell top.add_i (add)." > /dev/null
# Incorrectly sized wire
((../../yosys -f "verilog -sv" -qp "hierarchy -top top" - || true) <<EOT
((${YOSYS} -f "verilog -sv" -qp "hierarchy -top top" - || true) <<EOT
module add(input [7:0] a, input [7:0] b, output [7:0] q);
assign q = a + b;
endmodule
@ -56,7 +56,7 @@ EOT
) 2>&1 | grep -F "ERROR: Width mismatch between wire (7 bits) and port (8 bits) for implicit port connection \`b' of cell top.add_i (add)." > /dev/null
# Defaults
../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
${YOSYS} -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
module add(input [7:0] a = 8'd00, input [7:0] b = 8'd01, output [7:0] q);
assign q = a + b;
endmodule
@ -67,7 +67,7 @@ endmodule
EOT
# Parameterised module
../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
${YOSYS} -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
module add #(parameter N=3) (input [N-1:0] a = 8'd00, input [N-1:0] b = 8'd01, output [N-1:0] q);
assign q = a + b;
endmodule
@ -78,7 +78,7 @@ endmodule
EOT
# Parameterised blackbox module
../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:add" - <<EOT
${YOSYS} -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:add" - <<EOT
(* blackbox *)
module add #(parameter N=3) (input [N-1:0] a, b, output [N-1:0] q);
endmodule
@ -89,7 +89,7 @@ endmodule
EOT
# Parameterised blackbox module - incorrect width
((../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:add" - || true) <<EOT
((${YOSYS} -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:add" - || true) <<EOT
(* blackbox *)
module add #(parameter N=3) (input [N-1:0] a, b, output [N-1:0] q);
endmodule
@ -101,7 +101,7 @@ EOT
) 2>&1 | grep -F "ERROR: Width mismatch between wire (8 bits) and port (6 bits) for implicit port connection \`q' of cell top.add_i (add)." > /dev/null
# Mixed implicit and explicit 1
../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
${YOSYS} -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
module add(input [7:0] a, input [7:0] b, output [7:0] q);
assign q = a + b;
endmodule
@ -112,7 +112,7 @@ endmodule
EOT
# Mixed implicit and explicit 2
(../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
(${YOSYS} -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
module add(input [7:0] a, input [7:0] b, output [7:0] q);
assign q = a + b;
endmodule

10
tests/various/svalways.sh
View file

@ -3,7 +3,7 @@
trap 'echo "ERROR in svalways.sh" >&2; exit 1' ERR
# Good case
../../yosys -f "verilog -sv" -qp proc - <<EOT
${YOSYS} -f "verilog -sv" -qp proc - <<EOT
module top(input clk, en, d, output reg p, q, r);
always_ff @(posedge clk)
@ -19,7 +19,7 @@ endmodule
EOT
# Incorrect always_comb syntax
((../../yosys -f "verilog -sv" -qp proc -|| true) <<EOT
((${YOSYS} -f "verilog -sv" -qp proc -|| true) <<EOT
module top(input d, output reg q);
always_comb @(d)
@ -30,7 +30,7 @@ EOT
) 2>&1 | grep -F "<stdin>:3: ERROR: syntax error, unexpected '@'" > /dev/null
# Incorrect use of always_comb
((../../yosys -f "verilog -sv" -qp proc -|| true) <<EOT
((${YOSYS} -f "verilog -sv" -qp proc -|| true) <<EOT
module top(input en, d, output reg q);
always_comb
@ -41,7 +41,7 @@ EOT
) 2>&1 | grep -F "ERROR: Latch inferred for signal \`\\top.\\q' from always_comb process" > /dev/null
# Incorrect use of always_latch
((../../yosys -f "verilog -sv" -qp proc -|| true) <<EOT
((${YOSYS} -f "verilog -sv" -qp proc -|| true) <<EOT
module top(input en, d, output reg q);
always_latch
@ -52,7 +52,7 @@ EOT
) 2>&1 | grep -F "ERROR: No latch inferred for signal \`\\top.\\q' from always_latch process" > /dev/null
# Incorrect use of always_ff
((../../yosys -f "verilog -sv" -qp proc -|| true) <<EOT
((${YOSYS} -f "verilog -sv" -qp proc -|| true) <<EOT
module top(input en, d, output reg q);
always_ff @(*)