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https://github.com/YosysHQ/yosys
synced 2026-05-22 09:59:39 +00:00
Make out of tree build testing possible
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parent
5c6de04467
commit
c0779f488a
37 changed files with 131 additions and 119 deletions
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@ -24,6 +24,7 @@ warn_iverilog_git=false
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firrtl2verilog=""
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xfirrtl="../xfirrtl"
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abcprog="$toolsdir/../../yosys-abc"
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yosysprog="$toolsdir/../../yosys"
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exec {lock}<"$toolsdir"; flock "$lock" 1>&2
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if [ ! -f "$toolsdir/cmp_tbdata" -o "$toolsdir/cmp_tbdata.c" -nt "$toolsdir/cmp_tbdata" ]; then
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@ -31,7 +32,7 @@ if [ ! -f "$toolsdir/cmp_tbdata" -o "$toolsdir/cmp_tbdata.c" -nt "$toolsdir/cmp_
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fi
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flock -u "$lock"; exec {lock}>&-
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while getopts xmGl:wkjvref:s:p:n:S:I:A:-: opt; do
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while getopts xmGl:wkjvref:s:p:n:S:I:A:Y:-: opt; do
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case "$opt" in
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x)
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use_xsim=true ;;
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@ -70,6 +71,8 @@ while getopts xmGl:wkjvref:s:p:n:S:I:A:-: opt; do
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minclude_opts="$minclude_opts +incdir+$OPTARG" ;;
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A)
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abcprog="$OPTARG" ;;
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Y)
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yosysprog="$OPTARG" ;;
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-)
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case "${OPTARG}" in
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xfirrtl)
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@ -159,7 +162,7 @@ do
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fi
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if [ ! -f ../${bn}_tb.v ]; then
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"$toolsdir"/../../yosys -f "$frontend $include_opts -D_AUTOTB" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.${refext}
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$yosysprog -f "$frontend $include_opts -D_AUTOTB" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.${refext}
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else
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cp ../${bn}_tb.v ${bn}_tb.v
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fi
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@ -173,7 +176,7 @@ do
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test_count=0
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test_passes() {
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"$toolsdir"/../../yosys -b "verilog $backend_opts" -o ${bn}_syn${test_count}.v "$@"
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$yosysprog -b "verilog $backend_opts" -o ${bn}_syn${test_count}.v "$@"
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touch ${bn}.iverilog
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compile_and_run ${bn}_tb_syn${test_count} ${bn}_out_syn${test_count} \
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${bn}_tb.v ${bn}_syn${test_count}.v "${libs[@]}" \
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@ -203,7 +206,7 @@ do
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test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.${refext}
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if [ -n "$firrtl2verilog" ]; then
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if test -z "$xfirrtl" || ! grep "$fn" "$xfirrtl" ; then
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"$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep; proc; opt -nodffe -nosdff; fsm; opt; memory; opt -full -fine; pmuxtree" ${bn}_ref.${refext}
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$yosysprog -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep; proc; opt -nodffe -nosdff; fsm; opt; memory; opt -full -fine; pmuxtree" ${bn}_ref.${refext}
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$firrtl2verilog -i ${bn}_ref.fir -o ${bn}_ref.fir.v
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test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt -nodffe -nosdff; fsm; opt; memory; opt -full -fine" ${bn}_ref.fir.v
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fi
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