From c0709b1b4ed011b72c9fd2f65732e9b470d6566e Mon Sep 17 00:00:00 2001
From: nella <simontupy64@gmail.com>
Date: Mon, 15 Jun 2026 16:23:44 +0200
Subject: [PATCH] Fixup issue test.

---
 tests/proc/proc_dlatch.ys | 44 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/tests/proc/proc_dlatch.ys b/tests/proc/proc_dlatch.ys
index 3dba3076e..b45e9831b 100644
--- a/tests/proc/proc_dlatch.ys
+++ b/tests/proc/proc_dlatch.ys
@@ -87,3 +87,47 @@ EOT
 proc
 select -assert-count 1 t:$dlatch
 select -assert-count 0 t:$adlatch
+
+design -reset
+
+read_verilog -formal <<EOT
+module gold(input g, rn, d, zero, output reg q);
+	always @* if (~rn | g) q <= (~rn ? zero : d);
+	always @* assume(zero == 1'b0);
+endmodule
+module gate(input g, rn, d, zero, output reg q);
+	always @* if (~rn) q <= 1'b0; else if (g) q <= d;
+endmodule
+EOT
+
+proc
+select -assert-count 1 -module gold t:$dlatch
+select -assert-count 1 -module gate t:$adlatch
+select -clear
+equiv_make gold gate equiv
+hierarchy -top equiv
+clk2fflogic
+equiv_induct -set-assumes
+equiv_status -assert
+
+design -reset
+
+read_verilog -formal <<EOT
+module gold(input g, sn, d, one, output reg q);
+	always @* if (~sn | g) q <= (~sn ? one : d);
+	always @* assume(one == 1'b1);
+endmodule
+module gate(input g, sn, d, one, output reg q);
+	always @* if (~sn) q <= 1'b1; else if (g) q <= d;
+endmodule
+EOT
+
+proc
+select -assert-count 1 -module gold t:$dlatch
+select -assert-count 1 -module gate t:$adlatch
+select -clear
+equiv_make gold gate equiv
+hierarchy -top equiv
+clk2fflogic
+equiv_induct -set-assumes
+equiv_status -assert