3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-06-14 12:55:41 +00:00

timinginfo: special-case $specify2 in signorm invariant

This commit is contained in:
Emil J. Tywoniak 2026-03-26 19:42:33 +01:00
parent d33d048874
commit c06755f1bb
2 changed files with 4 additions and 5 deletions

View file

@ -1057,7 +1057,7 @@ void RTLIL::Cell::unsetPort(const RTLIL::IdString& portname)
void RTLIL::Cell::setPort(const RTLIL::IdString& portname, RTLIL::SigSpec signal)
{
bool is_input_port = false;
if (module->sig_norm_index != nullptr) {
if (module->sig_norm_index != nullptr && type != ID($specify2)) {
module->sig_norm_index->sigmap.apply(signal);
auto dir = port_dir(portname);