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Progress in FIRRTL back-end

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Clifford Wolf 2016-11-18 00:32:35 +01:00
parent 57966a619f
commit c051115e03
4 changed files with 55 additions and 5 deletions
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backends/firrtl/test.v Normal file
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module test(input clk, signed input [7:0] a, b, x, output [15:0] s, d, y, z, u, q);
assign s = a+{b[6:2], 2'b1}, d = a-b, y = x, z[7:0] = s+d, z[15:8] = s-d;
always @(posedge clk) q <= s ^ d ^ x;
endmodule