mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-23 06:13:41 +00:00
Add the $anyinit cell and the formalff pass
These can be used to protect undefined flip-flop initialization values from optimizations that are not sound for formal verification and can help mapping all solver-provided values in witness traces for flows that use different backends simultaneously.
This commit is contained in:
parent
c26b2bf543
commit
c0063288d6
16 changed files with 271 additions and 8 deletions
|
@ -1176,7 +1176,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
|
|||
return true;
|
||||
}
|
||||
|
||||
if (timestep > 0 && RTLIL::builtin_ff_cell_types().count(cell->type))
|
||||
if (timestep > 0 && (RTLIL::builtin_ff_cell_types().count(cell->type) || cell->type == ID($anyinit)))
|
||||
{
|
||||
FfData ff(nullptr, cell);
|
||||
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue