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Add the $anyinit cell and the formalff pass

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These can be used to protect undefined flip-flop initialization values
from optimizations that are not sound for formal verification and can
help mapping all solver-provided values in witness traces for flows that
use different backends simultaneously.
This commit is contained in:
Jannis Harder 2022-07-21 14:22:15 +02:00
parent c26b2bf543
commit c0063288d6
16 changed files with 271 additions and 8 deletions
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17
kernel/rtlil.cc
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@ -1632,6 +1632,13 @@ namespace {
return;
}
if (cell->type.in(ID($anyinit))) {
port(ID::D, param(ID::WIDTH));
port(ID::Q, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($equiv)) {
port(ID::A, 1);
port(ID::B, 1);
@ -3120,6 +3127,16 @@ RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, const RTLIL::S
return cell;
}
RTLIL::Cell* RTLIL::Module::addAnyinit(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, ID($anyinit));
cell->parameters[ID::WIDTH] = sig_q.size();
cell->setPort(ID::D, sig_d);
cell->setPort(ID::Q, sig_q);
cell->set_src_attribute(src);
return cell;
}
RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src)
{
RTLIL::SigSpec sig = addWire(NEW_ID, width);