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Fix abc9 with (* keep *) wires

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This commit is contained in:
Eddie Hung 2019-04-23 16:11:14 -07:00
parent 9d122d3c51
commit bfd71e0990
2 changed files with 52 additions and 6 deletions
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20
backends/aiger/xaiger.cc
View file

@ -133,6 +133,8 @@ struct XAigerWriter
init_map[initsig[i]] = initval[i] == State::S1; init_map[initsig[i]] = initval[i] == State::S1;
} }
bool keep = wire->attributes.count("\\keep");
for (int i = 0; i < GetSize(wire); i++) for (int i = 0; i < GetSize(wire); i++)
{ {
SigBit wirebit(wire, i); SigBit wirebit(wire, i);
@ -151,8 +153,10 @@ struct XAigerWriter
if (wire->port_input) if (wire->port_input)
input_bits.insert(bit); input_bits.insert(bit);
else if (keep)
input_bits.insert(wirebit);
if (wire->port_output) { if (wire->port_output || keep) {
if (bit != wirebit) if (bit != wirebit)
alias_map[wirebit] = bit; alias_map[wirebit] = bit;
output_bits.insert(wirebit); output_bits.insert(wirebit);
@ -338,10 +342,12 @@ struct XAigerWriter
for (auto bit : input_bits) { for (auto bit : input_bits) {
RTLIL::Wire *wire = bit.wire; RTLIL::Wire *wire = bit.wire;
// If encountering an inout port, then create a new wire with $inout.out // If encountering an inout port, or a keep-ed wire, then create a new wire
// suffix, make it a PO driven by the existing inout, and inherit existing // with $inout.out suffix, make it a PO driven by the existing inout, and
// inout's drivers // inherit existing inout's drivers
if (wire->port_input && wire->port_output && !undriven_bits.count(bit)) { if ((wire->port_input && wire->port_output && !undriven_bits.count(bit))
|| wire->attributes.count("\\keep")) {
log_assert(input_bits.count(bit) && output_bits.count(bit));
RTLIL::Wire *new_wire = module->wire(wire->name.str() + "$inout.out"); RTLIL::Wire *new_wire = module->wire(wire->name.str() + "$inout.out");
if (!new_wire) if (!new_wire)
new_wire = module->addWire(wire->name.str() + "$inout.out", GetSize(wire)); new_wire = module->addWire(wire->name.str() + "$inout.out", GetSize(wire));
@ -354,7 +360,9 @@ struct XAigerWriter
else if (alias_map.count(bit)) else if (alias_map.count(bit))
alias_map[new_bit] = alias_map.at(bit); alias_map[new_bit] = alias_map.at(bit);
else else
//log_abort();
alias_map[new_bit] = bit; alias_map[new_bit] = bit;
output_bits.erase(bit);
output_bits.insert(new_bit); output_bits.insert(new_bit);
} }
} }
@ -750,7 +758,7 @@ struct XAigerWriter
{ {
RTLIL::SigBit b(wire, i); RTLIL::SigBit b(wire, i);
if (input_bits.count(b)) { if (input_bits.count(b)) {
int a = aig_map.at(sig[i]); int a = aig_map.at(b);
log_assert((a & 1) == 0); log_assert((a & 1) == 0);
input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire)); input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
} }

38
tests/simple_abc9/abc9.v
View file

@ -104,3 +104,41 @@ always @(io or oe)
assign io[3:0] = oe ? ~latch[3:0] : 4'bz; assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz; assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
endmodule endmodule
module abc9_test015(input a, output b, input c);
assign b = ~a;
(* keep *) wire d;
assign d = ~c;
endmodule
module abc9_test016(input a, output b);
assign b = ~a;
(* keep *) reg c;
always @* c <= ~a;
endmodule
module abc9_test017(input a, output b);
assign b = ~a;
(* keep *) reg c;
always @* c = b;
endmodule
module abc9_test018(input a, output b, output c);
assign b = ~a;
(* keep *) wire [1:0] d;
assign c = &d;
endmodule
module abc9_test019(input a, output b);
assign b = ~a;
(* keep *) reg [1:0] c;
reg d;
always @* d <= &c;
endmodule
module abc9_test020(input a, output b);
assign b = ~a;
(* keep *) reg [1:0] c;
(* keep *) reg d;
always @* d <= &c;
endmodule