mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-06-05 00:20:52 +00:00
Code Activity

filterlib, read_liberty: add loopy retention cell formal equivalence test

Browse source
This commit is contained in:
Emil J. Tywoniak 2025-11-21 00:44:24 +01:00
parent b3112bf025
commit bfc957ee2d
8 changed files with 152 additions and 12 deletions
Download patch file Download diff file Expand all files Collapse all files

6
tests/liberty/unquoted.lib.verilogsim.ok
View file

@ -5,11 +5,9 @@ module dff1 (D, CLK, Q);
output Q;
assign Q = IQ; // IQ
always @(posedge CLK) begin
// (~D)
IQ <= (~D);
end
always @(posedge CLK) begin
// ~((~D))
IQN <= ~((~D));
end
endmodule
@ -20,11 +18,9 @@ module dff2 (D, CLK, Q);
output Q;
assign Q = IQ; // "IQ"
always @(posedge CLK) begin
// (~D)
IQ <= (~D);
end
always @(posedge CLK) begin
// ~((~D))
IQN <= ~((~D));
end
endmodule
@ -38,11 +34,9 @@ module dffe (D, EN, CLK, Q, QN);
output QN;
assign QN = IQN; // "IQN"
always @(negedge CLK) begin
// ((D&EN)|(IQ&(~EN)))
IQ <= ((D&EN)|(IQ&(~EN)));
end
always @(negedge CLK) begin
// ~(((D&EN)|(IQ&(~EN))))
IQN <= ~(((D&EN)|(IQ&(~EN))));
end
endmodule