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filterlib, read_liberty: add loopy retention cell formal equivalence test

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This commit is contained in:
Emil J. Tywoniak 2025-11-21 00:44:24 +01:00
parent b3112bf025
commit bfc957ee2d
8 changed files with 152 additions and 12 deletions
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2
tests/liberty/normal.lib.verilogsim.ok
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@ -58,7 +58,6 @@ module dff (D, CLK, RESET, PRESET, Q, QN);
IQ <= 1;
end
else begin
// D
IQ <= D;
end
end
@ -70,7 +69,6 @@ module dff (D, CLK, RESET, PRESET, Q, QN);
IQN <= 1;
end
else begin
// ~(D)
IQN <= ~(D);
end
end