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filterlib, read_liberty: add loopy retention cell formal equivalence test

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Emil J. Tywoniak 2025-11-21 00:44:24 +01:00
parent b3112bf025
commit bfc957ee2d
8 changed files with 152 additions and 12 deletions
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tests/liberty/dff.lib.verilogsim.ok
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@ -5,11 +5,9 @@ module dff (D, CLK, Q);
output Q;
assign Q = IQ; // IQ
always @(posedge CLK) begin
// D
IQ <= D;
end
always @(posedge CLK) begin
// ~(D)
IQN <= ~(D);
end
endmodule