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Move LSB-trimming functionality from wreduce to opt_expr

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This commit is contained in:
Eddie Hung 2019-08-06 15:25:50 -07:00
parent 84f52aee0d
commit bfc7164af7
2 changed files with 26 additions and 23 deletions
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25
passes/opt/opt_expr.cc
View file

@ -641,6 +641,31 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
did_something = true; did_something = true;
} }
} }
if (cell->type.in("$add", "$sub")) {
RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
RTLIL::SigSpec sig_y = cell->getPort("\\Y");
bool sub = cell->type == "$sub";
int i;
for (i = 0; i < GetSize(sig_y); i++) {
if (sig_b.at(i, State::Sx) == State::S0 && sig_a.at(i, State::Sx) != State::Sx)
module->connect(sig_y[i], sig_a[i]);
else if (!sub && sig_a.at(i, State::Sx) == State::S0 && sig_b.at(i, State::Sx) != State::Sx)
module->connect(sig_y[i], sig_b[i]);
else
break;
}
if (i > 0) {
cover_list("opt.opt_expr.fine", "$add", "$sub", cell->type.str());
cell->setPort("\\A", sig_a.extract_end(i));
cell->setPort("\\B", sig_b.extract_end(i));
cell->setPort("\\Y", sig_y.extract_end(i));
cell->fixup_parameters();
did_something = true;
}
}
} }
if (cell->type == "$reduce_xor" || cell->type == "$reduce_xnor" || cell->type == "$shift" || cell->type == "$shiftx" || if (cell->type == "$reduce_xor" || cell->type == "$reduce_xnor" || cell->type == "$shift" || cell->type == "$shiftx" ||

24
passes/opt/wreduce.cc
View file

@ -365,28 +365,6 @@ struct WreduceWorker
} }
} }
if (cell->type.in("$add", "$sub")) {
SigSpec A = mi.sigmap(cell->getPort("\\A"));
SigSpec B = mi.sigmap(cell->getPort("\\B"));
bool sub = cell->type == "$sub";
int i;
for (i = 0; i < GetSize(sig); i++) {
if (B.at(i, Sx) == S0 && A.at(i, Sx) != Sx)
module->connect(sig[i], A[i]);
else if (!sub && A.at(i, Sx) == S0 && B.at(i, Sx) != Sx)
module->connect(sig[i], B[i]);
else
break;
}
if (i > 0) {
cell->setPort("\\A", A.extract(i, -1));
cell->setPort("\\B", B.extract(i, -1));
sig.remove(0, i);
bits_removed += i;
}
}
if (GetSize(sig) == 0) { if (GetSize(sig) == 0) {
log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type)); log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
module->remove(cell); module->remove(cell);
@ -394,7 +372,7 @@ struct WreduceWorker
} }
if (bits_removed) { if (bits_removed) {
log("Removed %d bits (of %d) from port Y of cell %s.%s (%s).\n", log("Removed top %d bits (of %d) from port Y of cell %s.%s (%s).\n",
bits_removed, GetSize(sig) + bits_removed, log_id(module), log_id(cell), log_id(cell->type)); bits_removed, GetSize(sig) + bits_removed, log_id(module), log_id(cell), log_id(cell->type));
cell->setPort("\\Y", sig); cell->setPort("\\Y", sig);
did_something = true; did_something = true;