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Improve splitcells pass

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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
This commit is contained in:
Claire Xenia Wolf 2023-01-18 00:31:29 +01:00
parent 956c4e485a
commit bfc3c20cfb
1 changed files with 126 additions and 58 deletions
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74
passes/cmds/splitcells.cc
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@ -68,8 +68,8 @@ struct SplitcellsWorker
int split(Cell *cell, const std::string &format) int split(Cell *cell, const std::string &format)
{ {
if (!cell->type.in("$and", "$mux", "$not", "$or", "$pmux", "$xnor", "$xor")) return 0; if (cell->type.in("$and", "$mux", "$not", "$or", "$pmux", "$xnor", "$xor"))
{
SigSpec outsig = sigmap(cell->getPort(ID::Y)); SigSpec outsig = sigmap(cell->getPort(ID::Y));
if (GetSize(outsig) <= 1) return 0; if (GetSize(outsig) <= 1) return 0;
@ -133,6 +133,68 @@ struct SplitcellsWorker
module->remove(cell); module->remove(cell);
return GetSize(slices)-1; return GetSize(slices)-1;
} }
if (cell->type.in("$ff", "$dff", "$dffe", "$dffsr", "$dffsre", "$adff", "$adffe", "$aldffe",
"$sdff", "$sdffce", "$sdffe", "$dlatch", "$dlatchsr", "$adlatch"))
{
auto splitports = {ID::D, ID::Q, ID::AD, ID::SET, ID::CLR};
auto splitparams = {ID::ARST_VALUE, ID::SRST_VALUE};
SigSpec outsig = sigmap(cell->getPort(ID::Q));
if (GetSize(outsig) <= 1) return 0;
int width = GetSize(outsig);
std::vector<int> slices;
slices.push_back(0);
for (int i = 1; i < width; i++) {
auto &last_users = bit_users_db[outsig[slices.back()]];
auto &this_users = bit_users_db[outsig[i]];
if (last_users != this_users) slices.push_back(i);
}
if (GetSize(slices) <= 1) return 0;
slices.push_back(GetSize(outsig));
log("Splitting %s cell %s/%s into %d slices:\n", log_id(cell->type), log_id(module), log_id(cell), GetSize(slices)-1);
for (int i = 1; i < GetSize(slices); i++)
{
int slice_msb = slices[i]-1;
int slice_lsb = slices[i-1];
IdString slice_name = module->uniquify(cell->name.str() + (slice_msb == slice_lsb ?
stringf("%c%d%c", format[0], slice_lsb, format[1]) :
stringf("%c%d%c%d%c", format[0], slice_msb, format[2], slice_lsb, format[1])));
Cell *slice = module->addCell(slice_name, cell);
for (IdString portname : splitports) {
if (slice->hasPort(portname)) {
SigSpec sig = slice->getPort(portname);
sig = sig.extract(slice_lsb, slice_msb-slice_lsb+1);
slice->setPort(portname, sig);
}
}
for (IdString paramname : splitparams) {
if (slice->hasParam(paramname)) {
Const val = slice->getParam(paramname);
val = val.extract(slice_lsb, slice_msb-slice_lsb+1);
slice->setParam(paramname, val);
}
}
slice->setParam(ID::WIDTH, GetSize(slice->getPort(ID::Q)));
log(" slice %d: %s => %s\n", i, log_id(slice_name), log_signal(slice->getPort(ID::Q)));
}
module->remove(cell);
return GetSize(slices)-1;
}
return 0;
}
}; };
struct SplitcellsPass : public Pass { struct SplitcellsPass : public Pass {
@ -179,15 +241,21 @@ struct SplitcellsPass : public Pass {
for (auto module : design->selected_modules()) for (auto module : design->selected_modules())
{ {
SplitcellsWorker worker(module);
int count_split_pre = 0; int count_split_pre = 0;
int count_split_post = 0; int count_split_post = 0;
while (1) {
SplitcellsWorker worker(module);
bool did_something = false;
for (auto cell : module->selected_cells()) { for (auto cell : module->selected_cells()) {
int n = worker.split(cell, format); int n = worker.split(cell, format);
did_something |= (n != 0);
count_split_pre += (n != 0); count_split_pre += (n != 0);
count_split_post += n; count_split_post += n;
} }
if (!did_something)
break;
}
if (count_split_pre) if (count_split_pre)
log("Split %d cells in module %s into %d cell slices.\n", log("Split %d cells in module %s into %d cell slices.\n",