mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-26 18:45:34 +00:00
Add test to verify that the liberty format is properly parsed.
This commit is contained in:
parent
b7d7b377fd
commit
bf8aece4e4
5 changed files with 86 additions and 0 deletions
22
tests/liberty/dff.lib
Normal file
22
tests/liberty/dff.lib
Normal file
|
@ -0,0 +1,22 @@
|
|||
// Test library for different DFF function expressions
|
||||
|
||||
library(dff) {
|
||||
cell (dff) {
|
||||
area : 1;
|
||||
ff("IQ", "IQN") {
|
||||
next_state : "(D)";
|
||||
clocked_on : "CLK";
|
||||
}
|
||||
pin(D) {
|
||||
direction : input;
|
||||
}
|
||||
pin(CLK) {
|
||||
direction : input;
|
||||
}
|
||||
pin(Q) {
|
||||
direction: output;
|
||||
function : "IQ";
|
||||
}
|
||||
}
|
||||
|
||||
} /* end */
|
19
tests/liberty/dff.lib.filtered.ok
Normal file
19
tests/liberty/dff.lib.filtered.ok
Normal file
|
@ -0,0 +1,19 @@
|
|||
library(dff) {
|
||||
cell(dff) {
|
||||
area : 1 ;
|
||||
ff("IQ", "IQN") {
|
||||
next_state : "(D)" ;
|
||||
clocked_on : "CLK" ;
|
||||
}
|
||||
pin(D) {
|
||||
direction : input ;
|
||||
}
|
||||
pin(CLK) {
|
||||
direction : input ;
|
||||
}
|
||||
pin(Q) {
|
||||
direction : output ;
|
||||
function : "IQ" ;
|
||||
}
|
||||
}
|
||||
}
|
12
tests/liberty/dff.lib.verilogsim.ok
Normal file
12
tests/liberty/dff.lib.verilogsim.ok
Normal file
|
@ -0,0 +1,12 @@
|
|||
module dff (D, CLK, Q);
|
||||
reg "IQ", "IQN";
|
||||
input D;
|
||||
input CLK;
|
||||
output Q;
|
||||
assign Q = IQ; // "IQ"
|
||||
always @(posedge CLK) begin
|
||||
// "(D)"
|
||||
"IQ" <= (D);
|
||||
"IQN" <= ~((D));
|
||||
end
|
||||
endmodule
|
29
tests/liberty/dff.log.ok
Normal file
29
tests/liberty/dff.log.ok
Normal file
|
@ -0,0 +1,29 @@
|
|||
|
||||
-- Running command `dfflibmap -info -liberty dff.lib' --
|
||||
|
||||
1. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
|
||||
cell dff (noninv, pins=3, area=1.00) is a direct match for cell type $_DFF_P_.
|
||||
final dff cell mappings:
|
||||
unmapped dff cell: $_DFF_N_
|
||||
\dff _DFF_P_ (.CLK( C), .D( D), .Q( Q));
|
||||
unmapped dff cell: $_DFF_NN0_
|
||||
unmapped dff cell: $_DFF_NN1_
|
||||
unmapped dff cell: $_DFF_NP0_
|
||||
unmapped dff cell: $_DFF_NP1_
|
||||
unmapped dff cell: $_DFF_PN0_
|
||||
unmapped dff cell: $_DFF_PN1_
|
||||
unmapped dff cell: $_DFF_PP0_
|
||||
unmapped dff cell: $_DFF_PP1_
|
||||
unmapped dff cell: $_DFFE_NN_
|
||||
unmapped dff cell: $_DFFE_NP_
|
||||
unmapped dff cell: $_DFFE_PN_
|
||||
unmapped dff cell: $_DFFE_PP_
|
||||
unmapped dff cell: $_DFFSR_NNN_
|
||||
unmapped dff cell: $_DFFSR_NNP_
|
||||
unmapped dff cell: $_DFFSR_NPN_
|
||||
unmapped dff cell: $_DFFSR_NPP_
|
||||
unmapped dff cell: $_DFFSR_PNN_
|
||||
unmapped dff cell: $_DFFSR_PNP_
|
||||
unmapped dff cell: $_DFFSR_PPN_
|
||||
unmapped dff cell: $_DFFSR_PPP_
|
||||
dfflegalize command line: dfflegalize -cell $_DFF_P_ 01 t:$_DFF* t:$_SDFF*
|
|
@ -7,6 +7,10 @@ for x in *.lib; do
|
|||
../../yosys-filterlib - $x 2>/dev/null > $x.filtered
|
||||
../../yosys-filterlib -verilogsim $x > $x.verilogsim
|
||||
diff $x.filtered $x.filtered.ok && diff $x.verilogsim $x.verilogsim.ok
|
||||
if [[ -e ${x%.lib}.log.ok ]]; then
|
||||
../../yosys -p "dfflibmap -info -liberty ${x}" -TqqQl ${x%.lib}.log
|
||||
diff ${x%.lib}.log ${x%.lib}.log.ok
|
||||
fi
|
||||
done || exit 1
|
||||
|
||||
for x in *.ys; do
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue