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Add test to verify that the liberty format is properly parsed.

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Mike Inouye 2025-04-23 18:40:35 +00:00
parent b7d7b377fd
commit bf8aece4e4
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tests/liberty/dff.lib.verilogsim.ok Normal file
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module dff (D, CLK, Q);
reg "IQ", "IQN";
input D;
input CLK;
output Q;
assign Q = IQ; // "IQ"
always @(posedge CLK) begin
// "(D)"
"IQ" <= (D);
"IQN" <= ~((D));
end
endmodule