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Merge pull request #47 from alaindargelas/splitfanout_test
Add splitfanout tests
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alaindargelas
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commit
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388
tests/various/splitfanout.ys
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388
tests/various/splitfanout.ys
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# Basic accepted case
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# Cell has fanout into module output port
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read_verilog <<EOT
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module top(input x, input y, input z, output o, output p);
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wire a = !x;
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assign o = a + y;
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assign p = a + z;
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endmodule
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EOT
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proc -noopt
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opt_clean -purge
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equiv_opt -assert splitfanout
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design -load preopt
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select -assert-count 1 t:$logic_not
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design -load postopt
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select -assert-count 2 t:$logic_not
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design -reset
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read_verilog <<EOT
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module top(input [1:0] x, input [1:0] y, input [1:0] z, output [1:0] o, output [1:0] p);
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wire [1:0] a = !x;
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assign o = a + y;
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assign p = a + z;
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endmodule
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EOT
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proc -noopt
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opt_clean -purge
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equiv_opt -assert splitfanout
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design -load preopt
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select -assert-count 1 t:$logic_not
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design -load postopt
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select -assert-count 2 t:$logic_not
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design -reset
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# Chain of length 1 accepted
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# Cell has fanout into cell input ports
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read_verilog <<EOT
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module top(input a, input b, output c);
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reg x = a & b;
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assign c = x & x;
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endmodule
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EOT
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proc -noopt
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opt_clean -purge
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equiv_opt -assert splitfanout
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design -load preopt
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select -assert-count 2 t:$and
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design -load postopt
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select -assert-count 3 t:$and
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design -reset
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read_verilog <<EOT
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module top(input [1:0] a, input [1:0] b, output [1:0] c);
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reg [1:0] x = a & b;
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assign c = x & x;
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endmodule
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EOT
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proc -noopt
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opt_clean -purge
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equiv_opt -assert splitfanout
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design -load preopt
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select -assert-count 2 t:$and
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design -load postopt
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select -assert-count 3 t:$and
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design -reset
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# Chain of length 3 accepted
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# Cell has fanout into cell input ports
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# Schematic: =D<D<D<D-
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# Exponential cell count growth!
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read_verilog <<EOT
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module top(input a, input b, output c);
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reg x1 = a & b;
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reg x2 = x1 & x1;
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reg x3 = x2 & x2;
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assign c = x3 & x3;
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endmodule
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EOT
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proc -noopt
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equiv_opt -assert splitfanout
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design -load preopt
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select -assert-count 4 t:$and
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design -load postopt
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select -assert-count 15 t:$and
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design -reset
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read_verilog <<EOT
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module top(input [1:0] a, input [1:0] b, output [1:0] c);
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reg [1:0] x1 = a & b;
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reg [1:0] x2 = x1 & x1;
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reg [1:0] x3 = x2 & x2;
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assign c = x3 & x3;
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endmodule
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EOT
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proc -noopt
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equiv_opt -assert splitfanout
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design -load preopt
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select -assert-count 4 t:$and
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design -load postopt
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select -assert-count 15 t:$and
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design -reset
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# Basic accepted case transformed if fanout under limit
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read_verilog <<EOT
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module top(input x, input y, input z, output o, output p);
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wire a = !x;
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assign o = a + y;
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assign p = a + z;
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endmodule
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EOT
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proc -noopt
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opt_clean -purge
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equiv_opt -assert splitfanout -limit 2
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design -load preopt
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select -assert-count 1 t:$logic_not
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design -load postopt
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select -assert-count 2 t:$logic_not
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design -reset
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# Basic accepted case transformed if fanout over limit
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read_verilog <<EOT
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module top(input x, input y, input z, output o, output p);
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wire a = !x;
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assign o = a + y;
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assign p = a + z;
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endmodule
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EOT
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proc -noopt
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opt_clean -purge
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equiv_opt -assert splitfanout -limit 1
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design -load preopt
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select -assert-count 1 t:$logic_not
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design -load postopt
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select -assert-count 1 t:$logic_not
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design -reset
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# If some fanout over limit, module is *partially* transformed
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read_verilog <<EOT
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module top(input x1, input x2, input x3, output o1, output o2, output o3, output o4, output o5);
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wire a = !x1;
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wire b = x2 & x3;
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assign o1 = a;
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assign o2 = a;
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assign o3 = b;
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assign o4 = b;
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assign o5 = b;
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endmodule
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EOT
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proc -noopt
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opt_clean -purge
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equiv_opt -assert splitfanout -limit 2
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design -load preopt
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select -assert-count 1 t:$logic_not
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select -assert-count 1 t:$and
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design -load postopt
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select -assert-count 2 t:$logic_not
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select -assert-count 1 t:$and
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design -reset
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read_verilog <<EOT
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module top(input [1:0] x1, input [1:0] x2, input [1:0] x3, output [1:0] o1, output [1:0] o2, output [1:0] o3, output [1:0] o4, output [1:0] o5);
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wire [1:0] a = !x1;
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wire [1:0] b = x2 & x3;
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assign o1 = a;
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assign o2 = a;
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assign o3 = b;
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assign o4 = b;
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assign o5 = b;
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endmodule
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EOT
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proc -noopt
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opt_clean -purge
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equiv_opt -assert splitfanout -limit 2
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design -load preopt
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select -assert-count 1 t:$logic_not
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select -assert-count 1 t:$and
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design -load postopt
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select -assert-count 2 t:$logic_not
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select -assert-count 1 t:$and
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design -reset
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# Only selected cells are split
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read_verilog <<EOT
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module top(input x1, input x2, output o1, output o2, output o3, output o4);
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wire a = !x1;
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wire b = !x2;
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assign o1 = a;
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assign o2 = a;
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assign o3 = b;
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assign o4 = b;
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endmodule
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EOT
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proc -noopt
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opt_clean -purge
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# Two nots in module
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select -assert-count 2 t:$logic_not
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# Selection used for splitfanout only selects one
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select -assert-count 1 w:x1 %co t:$logic_not %i
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equiv_opt -assert splitfanout -limit 2 w:x1 %co
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design -load preopt
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select -assert-count 2 t:$logic_not
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design -load postopt
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select -assert-count 3 t:$logic_not
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design -reset
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read_verilog <<EOT
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module top(input [1:0] x1, input [1:0] x2, output [1:0] o1, output [1:0] o2, output [1:0] o3, output [1:0] o4);
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wire [1:0] a = !x1;
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wire [1:0] b = !x2;
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assign o1 = a;
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assign o2 = a;
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assign o3 = b;
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assign o4 = b;
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endmodule
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EOT
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proc -noopt
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opt_clean -purge
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# Two nots in module
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select -assert-count 2 t:$logic_not
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# Selection used for splitfanout only selects one
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select -assert-count 1 w:x1 %co t:$logic_not %i
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equiv_opt -assert splitfanout -limit 2 w:x1 %co
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design -load preopt
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select -assert-count 2 t:$logic_not
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design -load postopt
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select -assert-count 3 t:$logic_not
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design -reset
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# Only selected cells are split
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read_verilog <<EOT
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module top(input x1, input x2, output o1, output o2, output o3, output o4);
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wire a = !x1;
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wire b = !x2;
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assign o1 = a;
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assign o2 = a;
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assign o3 = b;
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assign o4 = b;
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endmodule
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EOT
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proc -noopt
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opt_clean -purge
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# Two nots in module
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select -assert-count 2 t:$logic_not
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# Selection used for splitfanout only selects one
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select -assert-count 1 w:x1 %co t:$logic_not %i
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equiv_opt -assert splitfanout -limit 2 w:x1 %co
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design -load preopt
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select -assert-count 2 t:$logic_not
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design -load postopt
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select -assert-count 3 t:$logic_not
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design -reset
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read_verilog <<EOT
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module top(input [1:0] x1, input [1:0] x2, output [1:0] o1, output [1:0] o2, output [1:0] o3, output [1:0] o4);
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wire [1:0] a = !x1;
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wire [1:0] b = !x2;
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assign o1 = a;
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assign o2 = a;
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assign o3 = b;
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assign o4 = b;
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endmodule
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EOT
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proc -noopt
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opt_clean -purge
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# Two nots in module
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select -assert-count 2 t:$logic_not
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# Selection used for splitfanout only selects one
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select -assert-count 1 w:x1 %co t:$logic_not %i
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equiv_opt -assert splitfanout -limit 2 w:x1 %co
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design -load preopt
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select -assert-count 2 t:$logic_not
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design -load postopt
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select -assert-count 3 t:$logic_not
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design -reset
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# Multi-bit cells get split
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read_verilog <<EOT
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module top(input [1:0] a, input [1:0] b, output [1:0] c, output [1:0] d);
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reg [1:0] x = a & b;
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assign c = x;
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assign d = x;
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endmodule
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EOT
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proc -noopt
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equiv_opt -assert splitfanout
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design -load preopt
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select -assert-count 1 t:$and
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design -load postopt
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select -assert-count 2 t:$and
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design -reset
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# Multi-bit cells with different bit users don't get split
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read_verilog <<EOT
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module top(input [1:0] a, input [1:0] b, output c, output d);
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reg [1:0] x = a & b;
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assign c = x[0];
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assign d = x[1];
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endmodule
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EOT
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proc -noopt
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equiv_opt -assert splitfanout
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design -load preopt
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select -assert-count 1 t:$and
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design -load postopt
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select -assert-count 1 t:$and
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design -reset
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# Cells with some bits unused don't get split
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read_verilog <<EOT
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module top(input [1:0] a, input [1:0] b, output c, output d);
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reg [1:0] x = a & b;
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assign c = x[0];
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assign d = x[0];
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endmodule
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EOT
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proc -noopt
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equiv_opt -assert splitfanout
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design -load preopt
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select -assert-count 1 t:$and
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design -load postopt
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select -assert-count 1 t:$and
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design -reset
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# Cell has fanout into both module output port and cell input
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read_verilog <<EOT
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module top(input x, input y, output o, output p);
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wire a = !x;
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assign o = a + y;
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assign p = a;
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endmodule
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EOT
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proc -noopt
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opt_clean -purge
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equiv_opt -assert splitfanout
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design -load preopt
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select -assert-count 1 t:$logic_not
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design -load postopt
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select -assert-count 2 t:$logic_not
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design -reset
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read_verilog <<EOT
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module top(input [1:0] x, input [1:0] y, output [1:0] o, output [1:0] p);
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wire [1:0] a = !x;
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assign o = a + y;
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assign p = a;
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endmodule
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EOT
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proc -noopt
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opt_clean -purge
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equiv_opt -assert splitfanout
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design -load preopt
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select -assert-count 1 t:$logic_not
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design -load postopt
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select -assert-count 2 t:$logic_not
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design -reset
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# Cell is a blackbox
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read_verilog <<EOT
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(* blackbox *)
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module MY_AND(input A, B, output Y);
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endmodule
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module top(input A, B, output Y, Z);
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wire X;
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MY_AND a(A,B,X);
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assign Y = X;
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assign Z = X;
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endmodule
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EOT
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proc -noopt
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hierarchy
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select -assert-count 1 t:MY_AND
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splitfanout
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select -assert-count 2 t:MY_AND
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design -reset
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# A less trivial design
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read_verilog ../sat/alu.v
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proc -noopt
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equiv_opt -assert splitfanout
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design -load preopt
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select -assert-count 5 t:$dff
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design -load postopt
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select -assert-count 8 t:$dff
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design -reset
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# Booth-encoded 4x4->8 multiplier smoke test
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read_verilog <<EOT
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module top(input [3:0] A, input [3:0] B, output [7:0] Y);
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assign Y = A * B;
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endmodule
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EOT
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booth
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equiv_opt -assert splitfanout
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design -reset
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