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Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff

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Eddie Hung 2019-11-22 17:00:35 -08:00
commit bf7d36627e
1 changed files with 9 additions and 8 deletions
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17
passes/techmap/clkpart.cc
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@ -58,7 +58,7 @@ struct ClkPartPass : public Pass {
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
log_header(design, "Executing CLKPART pass (TODO).\n");
log_header(design, "Executing CLKPART pass (partition design according to clock domain).\n");
log_push();
clear_flags();
@ -233,15 +233,16 @@ struct ClkPartPass : public Pass {
std::get<0>(it.first) ? "" : "!", log_signal(std::get<1>(it.first)),
std::get<2>(it.first) ? "" : "!", log_signal(std::get<3>(it.first)));
for (auto &it : assigned_cells) {
RTLIL::Selection sel(false);
sel.selected_members[mod->name] = pool<IdString>(it.second.begin(), it.second.end());
if (assigned_cells.size() > 1)
for (auto &it : assigned_cells) {
RTLIL::Selection sel(false);
sel.selected_members[mod->name] = pool<IdString>(it.second.begin(), it.second.end());
RTLIL::IdString submod = stringf("%s.%s", mod->name.c_str(), NEW_ID.c_str());
Pass::call_on_selection(design, sel, stringf("submod -name %s", submod.c_str()));
RTLIL::IdString submod = stringf("%s.%s", mod->name.c_str(), NEW_ID.c_str());
Pass::call_on_selection(design, sel, stringf("submod -name %s", submod.c_str()));
design->module(submod)->set_bool_attribute(ID(clkpart));
}
design->module(submod)->set_bool_attribute(ID(clkpart));
}
}
}