mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-14 09:56:16 +00:00
Code Activity

Merge pull request #3341 from mmicko/unused_vars

Browse source 
Remove set but unused variable
This commit is contained in:
Miodrag Milanović 2022-05-27 14:45:35 +02:00 • committed by GitHub
commit bf78041e89
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
1 changed files with 0 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

4
kernel/consteval.h
View file

@ -146,7 +146,6 @@ struct ConstEval
if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_), ID($_NMUX_))) if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_), ID($_NMUX_)))
{ {
std::vector<RTLIL::SigSpec> y_candidates; std::vector<RTLIL::SigSpec> y_candidates;
int count_maybe_set_s_bits = 0;
int count_set_s_bits = 0; int count_set_s_bits = 0;
if (!eval(sig_s, undef, cell)) if (!eval(sig_s, undef, cell))
@ -160,9 +159,6 @@ struct ConstEval
if (s_bit == RTLIL::State::Sx || s_bit == RTLIL::State::S1) if (s_bit == RTLIL::State::Sx || s_bit == RTLIL::State::S1)
y_candidates.push_back(b_slice); y_candidates.push_back(b_slice);
if (s_bit == RTLIL::State::S1 || s_bit == RTLIL::State::Sx)
count_maybe_set_s_bits++;
if (s_bit == RTLIL::State::S1) if (s_bit == RTLIL::State::S1)
count_set_s_bits++; count_set_s_bits++;
} }