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Merge pull request #5497 from YosysHQ/krys/abc_done

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Fix ABC completion detection edge case
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KrystalDelusion 2025-11-22 09:37:50 +13:00 • committed by GitHub
commit bf70581efa
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4 changed files with 22 additions and 1 deletions
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2
passes/techmap/abc.cc
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@ -1064,7 +1064,7 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module
abc_script += stringf("; write_blif %s/output.blif", run_abc.tempdir_name);
abc_script = add_echos_to_abc_cmd(abc_script);
#if defined(__linux__) && !defined(YOSYS_DISABLE_SPAWN)
abc_script += "; echo \"YOSYS_ABC_DONE\"\n";
abc_script += "; echo; echo \"YOSYS_ABC_DONE\"\n";
#endif
for (size_t i = 0; i+1 < abc_script.size(); i++)

2
tests/techmap/bug5495.abc Normal file
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@ -0,0 +1,2 @@
fraig_store; fraig_restore

12
tests/techmap/bug5495.sh Executable file
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@ -0,0 +1,12 @@
#!/usr/bin/env bash
if ! which timeout ; then
echo "No 'timeout', skipping test"
exit 0
fi
if ! timeout 5 ../../yosys bug5495.v -p 'hierarchy; techmap; abc -script bug5495.abc' ; then
echo "Yosys failed to complete"
exit 1
fi

7
tests/techmap/bug5495.v Normal file
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@ -0,0 +1,7 @@
module simple(I1, I2, O);
input wire I1;
input wire I2;
output wire O;
assign O = I1 | I2;
endmodule