mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-30 19:22:31 +00:00
Code Activity

Fixed undef extend for bitwise binary ops (bugs in simplemap and satgen)

Browse source
This commit is contained in:
Clifford Wolf 2013-12-29 17:39:49 +01:00
parent 74d0de3b74
commit bf607df6d5
2 changed files with 10 additions and 13 deletions
Download patch file Download diff file Expand all files Collapse all files

19
kernel/satgen.h
View file

@ -121,11 +121,10 @@ struct SatGen
return ez->expression(ezSAT::OpAnd, eq_bits); return ez->expression(ezSAT::OpAnd, eq_bits);
} }
void extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, RTLIL::Cell *cell, size_t y_width = 0, bool undef_mode = false) void extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, RTLIL::Cell *cell, size_t y_width = 0, bool forced_signed = false)
{ {
log_assert(!undef_mode || model_undef); bool is_signed = forced_signed;
bool is_signed = undef_mode; if (!forced_signed && cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters.count("\\B_SIGNED") > 0)
if (!undef_mode && cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters.count("\\B_SIGNED") > 0)
is_signed = cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool(); is_signed = cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool();
while (vec_a.size() < vec_b.size() || vec_a.size() < y_width) while (vec_a.size() < vec_b.size() || vec_a.size() < y_width)
vec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->FALSE); vec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->FALSE);
@ -133,18 +132,16 @@ struct SatGen
vec_b.push_back(is_signed && vec_b.size() > 0 ? vec_b.back() : ez->FALSE); vec_b.push_back(is_signed && vec_b.size() > 0 ? vec_b.back() : ez->FALSE);
} }
void extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, std::vector<int> &vec_y, RTLIL::Cell *cell, bool undef_mode = false) void extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, std::vector<int> &vec_y, RTLIL::Cell *cell, bool forced_signed = false)
{ {
log_assert(!undef_mode || model_undef); extendSignalWidth(vec_a, vec_b, cell, vec_y.size(), forced_signed);
extendSignalWidth(vec_a, vec_b, cell, vec_y.size(), undef_mode);
while (vec_y.size() < vec_a.size()) while (vec_y.size() < vec_a.size())
vec_y.push_back(ez->literal()); vec_y.push_back(ez->literal());
} }
void extendSignalWidthUnary(std::vector<int> &vec_a, std::vector<int> &vec_y, RTLIL::Cell *cell, bool undef_mode = false) void extendSignalWidthUnary(std::vector<int> &vec_a, std::vector<int> &vec_y, RTLIL::Cell *cell, bool forced_signed = false)
{ {
log_assert(!undef_mode || model_undef); bool is_signed = forced_signed || (cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters["\\A_SIGNED"].as_bool());
bool is_signed = undef_mode || (cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters["\\A_SIGNED"].as_bool());
while (vec_a.size() < vec_y.size()) while (vec_a.size() < vec_y.size())
vec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->FALSE); vec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->FALSE);
while (vec_y.size() < vec_a.size()) while (vec_y.size() < vec_a.size())
@ -222,7 +219,7 @@ struct SatGen
std::vector<int> undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep); std::vector<int> undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->connections.at("\\B"), timestep); std::vector<int> undef_b = importUndefSigSpec(cell->connections.at("\\B"), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep); std::vector<int> undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep);
extendSignalWidth(undef_a, undef_b, undef_y, cell, true); extendSignalWidth(undef_a, undef_b, undef_y, cell, false);
if (cell->type == "$and" || cell->type == "$_AND_") { if (cell->type == "$and" || cell->type == "$_AND_") {
std::vector<int> a0 = ez->vec_and(ez->vec_not(a), ez->vec_not(undef_a)); std::vector<int> a0 = ez->vec_and(ez->vec_not(a), ez->vec_not(undef_a));

4
passes/techmap/simplemap.cc
View file

@ -77,11 +77,11 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
int width = cell->parameters.at("\\Y_WIDTH").as_int(); int width = cell->parameters.at("\\Y_WIDTH").as_int();
RTLIL::SigSpec sig_a = cell->connections.at("\\A"); RTLIL::SigSpec sig_a = cell->connections.at("\\A");
sig_a.extend(width, cell->parameters.at("\\A_SIGNED").as_bool()); sig_a.extend_u0(width, cell->parameters.at("\\A_SIGNED").as_bool());
sig_a.expand(); sig_a.expand();
RTLIL::SigSpec sig_b = cell->connections.at("\\B"); RTLIL::SigSpec sig_b = cell->connections.at("\\B");
sig_b.extend(width, cell->parameters.at("\\B_SIGNED").as_bool()); sig_b.extend_u0(width, cell->parameters.at("\\B_SIGNED").as_bool());
sig_b.expand(); sig_b.expand();
RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); RTLIL::SigSpec sig_y = cell->connections.at("\\Y");