mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-05 22:06:04 +00:00
Make SigSpec::is_wire/is_chunk/is_fully_const use chunk iterator
This commit is contained in:
parent
fd7b4f4a8b
commit
bf4cfbd72d
1 changed files with 12 additions and 6 deletions
|
|
@ -5401,22 +5401,28 @@ bool RTLIL::SigSpec::is_wire() const
|
||||||
{
|
{
|
||||||
cover("kernel.rtlil.sigspec.is_wire");
|
cover("kernel.rtlil.sigspec.is_wire");
|
||||||
|
|
||||||
pack();
|
Chunks cs = chunks();
|
||||||
return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
|
auto it = cs.begin();
|
||||||
|
if (it == cs.end())
|
||||||
|
return false;
|
||||||
|
const RTLIL::SigChunk &chunk = *it;
|
||||||
|
return chunk.wire && chunk.wire->width == width_ && ++it == cs.end();
|
||||||
}
|
}
|
||||||
|
|
||||||
bool RTLIL::SigSpec::is_chunk() const
|
bool RTLIL::SigSpec::is_chunk() const
|
||||||
{
|
{
|
||||||
cover("kernel.rtlil.sigspec.is_chunk");
|
cover("kernel.rtlil.sigspec.is_chunk");
|
||||||
|
|
||||||
pack();
|
Chunks cs = chunks();
|
||||||
return GetSize(chunks_) == 1;
|
auto it = cs.begin();
|
||||||
|
if (it == cs.end())
|
||||||
|
return false;
|
||||||
|
return ++it == cs.end();
|
||||||
}
|
}
|
||||||
|
|
||||||
bool RTLIL::SigSpec::known_driver() const
|
bool RTLIL::SigSpec::known_driver() const
|
||||||
{
|
{
|
||||||
pack();
|
for (auto &chunk : chunks())
|
||||||
for (auto &chunk : chunks_)
|
|
||||||
if (chunk.is_wire() && !chunk.wire->known_driver())
|
if (chunk.is_wire() && !chunk.wire->known_driver())
|
||||||
return false;
|
return false;
|
||||||
return true;
|
return true;
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue