mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 06:03:23 +00:00
Code Activity

Merge branch 'YosysHQ:main' into main

Browse source
This commit is contained in:
Akash Levy 2024-10-11 15:40:49 -07:00 • committed by GitHub
commit bf4b7ec0ea
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
1 changed files with 1 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/techmap/cellmatch.cc
View file

@ -223,7 +223,7 @@ struct CellmatchPass : Pass {
for (auto bit : outputs) { for (auto bit : outputs) {
log_assert(bit.is_wire()); log_assert(bit.is_wire());
bit.wire->attributes[ID(p_class)] = p_class(inputs.size(), luts[no]); bit.wire->attributes[ID(p_class)] = p_class(inputs.size(), luts[no]);
bit.wire->attributes[ID(lut)] = luts[no++]; bit.wire->attributes[ID(lut)] = Const(luts[no++], 1 << inputs.size());
} }
} }