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https://github.com/YosysHQ/yosys
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No operator optimization, but it passes all tests
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0ee2277d4f
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5 changed files with 25 additions and 8 deletions
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@ -92,7 +92,7 @@ generate_tests() {
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if [[ $do_sv = true ]]; then
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for x in *.sv; do
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if [ ! -f "${x%.sv}.ys" ]; then
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generate_ys_test "$x" "-p \"prep -top top; async2sync; select top; sat -enable_undef -verify -prove-asserts\" $yosys_args"
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generate_ys_test "$x" "-p \"prep -top top; async2sync; sat -enable_undef -verify -prove-asserts\" $yosys_args"
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fi;
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done
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fi;
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@ -2,8 +2,6 @@
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## Disabled
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<!-- - `import_warning_operator`: no VHDL -->
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<!-- - `mixed_flist`: no VHDL -->
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- `memory_semantics`: relies on initial values being retained, which we do not want
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- `rom_case`: we need different behavior for multi-port memories
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- `blackbox*`: we need different behavior for parametrized blackboxes
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